On-chip microprocessor instruction decoder having hardware for selectively bypassing on-chip circuitry used to decipher encrypted instruction codes

• US 4,633,388 A
• Filed: 01/18/1984
• Issued: 12/30/1986
• Est. Priority Date: 01/18/1984
• Status: Expired due to Term

• Current Assignee: Siemens Corporate Research & Support, Inc. (Siemens AG)
• Original Assignee: Siemens Corporate Research & Support, Inc. (Siemens AG)
• Inventors: Chiu, Ming-Yee
• Primary Examiner(s): Williams, Jr., Archie E.
• Application Number:
  US06/571,771
• Time in Patent Office: 1,077 Days
• Field of Search: 364/200, 364/900, 178/22.08, 178/22.09, 179/1.5 R, 358/114, 358/122
• US Class Current: 712/208
• CPC Class Codes: G06F 21/123 by using dedicated hardware, e.g. dongles, smart cards, cryptographic processors, global positioning systems [GPS] devices
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields

Abstract

A microprocessor has on-chip hardware for protecting software against unauthorized use. The microprocessor includes a decoder for deciphering software instruction codes prior to their execution by the microprocessor. The instruction codes are enciphered in a unique way so that they can only be executed by the specific microprocessor for which they are intended.

Claims

1. A microprocessor formed on an integrated circuit and adapted to execute the instructions of a specific instruction set, each instruction in said set being defined by a prescribed, digital instruction code, said microprocessor comprising, in combination:

(a) means, having a plurality of first inputs and responsive to said instruction codes applied to said first inputs, for executing the instructions defined by said instruction codes;

(b) instruction code queuing means, having a plurality of first outputs each connected to one of said first inputs of said instruction executing means, for receiving, storing and applying successive instruction codes to said first inputs, said queuing means including a decoder means for translating enciphered instruction codes into said prescribed, digital instruction codes; and

said decoder means including

(1) deciphering means for converting instruction codes; and

(2) bypassing means, connected to said deciphering means, for directing enciphered instruction codes through said deciphering means and directing non-enciphered instruction codes around said deciphering means and said bypassing means including switching means, arranged to receive instruction codes, for selecting a path for said instruction codes either to said deciphering means or around said deciphering means; and

said switching means is responsive to said instruction codes for selecting said path.

2. The microprocessor defined in claim 1, wherein said instruction code queing means has a plurality of second inputs and a buffer memory, coupled between said second inputs and said first outputs, for temporarily storing said instruction codes, said decoder means being connected in series with said buffer memory.

3. The microprocessor defined in claim 1, wherein said decoder means is programmable.

4. The microprocessor defined in claim 1, wherein said instruction codes received by said code queue are enciphered in a manner unique to said microprocessor.

5. The microprocessor defined in claim 1, wherein said switch means is responsive to specific ones of said instruction codes for selecting said path.

6. The microprocessor defined in claim 1, wherein said switch means is responsive to the presence or absence of enciphered instruction codes for selecting said path.