Self-configuring digital processor system with logical arbiter

• US 4,633,392 A
• Filed: 04/22/1985
• Issued: 12/30/1986
• Est. Priority Date: 04/05/1982
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McGrath, John, Conrad, Marvin C., Vincent, Geoffrey P. F., Ing-Simmons, Nicholas K. D.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/725,512
• Time in Patent Office: 617 Days
• Field of Search: 364/200, 364/900
• US Class Current: 710/104
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00

Abstract

A digital processor system including several function modules where each modules includes circuitry to perform at least one computational task and circuitry to transfer information containing that module'"'"'s respective computational task capability to a logical arbiter upon initialization. Each module further includes circuitry to interface to the logical arbiter upon initialization to determine that module'"'"'s address. Further disclosed is an information bus that connects all function modules together with the logical arbiter. The presence of the logical arbiter provides for a self-configuration capability upon initialization.

Claims

1. A data processing system comprising:

an information bus for transferring data;

a logical arbiter memory means connected for transfer of data to and from said information bus, for storing therein a global function table of function names together with their corresponding information bus access address; and

a plurality of function modules each connected for transfer of data to and from said information bus in response to function requests, each function module having (1) function means to perform at least one computational function in response to a corresponding function request on said information bus directed to a corresponding information bus access address, each such computational function having a corresponding function name, and (2) initialization means actuated upon each initial application of electric power to said function module for assigning an information bus access address for access to each such computational function via said information bus, said information bus access address assigned to a particular function name dependent upon the order of initialization of said function module, and for transmitting via said information bus said function name and said corresponding information bus access address of each such computational function to said logical arbiter memory means for storage in said global function table.

2. A data processing system as claimed in claim 1 wherein:

at least one function module includes means for requesting a computational function from another module by accessing said global function table via said information bus for recalling from said global function table the information bus access address of a function name corresponding to the desired computational function and transmitting a function request via said information bus to said recalled information bus access address.

3. A data processing system comprising:

an information bus for transferring data;

a logical arbiter memory means connected for transfer of data to and from said information bus, having an information bus access address assignment means for assigning information bus access addresses in a predetermined order, a global function table for storing therein function names together with their corresponding information bus access address, and a function address means for transmitting said information bus access address corresponding to a function name in response to a function address request on said information bus; and

a plurality of function modules each connected for transfer of data to and from said information bus in response to function requests, each function module having (1) function means to perform at least one computational function in response to a corresponding function request on said information bus directed to a corresponding information bus access address assigned by said information bus access address assignment means, each such computational function having a corresponding function name, and (2) initialization means actuated upon each initial application of electric power to said function module for transmitting via said information bus said function name of each such computational function to said logical arbiter memory means for storage in said global function table.

4. A data processing system as claimed in claim 3 wherein:

at least one function module includes means for requesting a computational function from another module by accessing said global function table via said information bus for recalling from said global function table the information bus access address of a function name corresponding to the desired computational function and transmitting a function request via said information bus to said recalled information bus access address.

5. A data processing system comprising:

an information bus for transferring data;

a logical arbiter memory means connected for transfer of data to and from said information bus, for storing therein a global function table of function names together with their corresponding information bus access address and having an initialization counter for storing a count which is set to a predetermined initializatin count upon each initial application of electric power to said logical arbiter memory means;

a plurality of function modules each connected for transfer of data to and from said information bus in response to function requests, each function module having

(1) a bus priority for determining priority of control of data transfer via said information bus,

(2) function means to perform a computational function in response to a corresponding function request on said information bus directed to a corresponding information bus access address, said computational function having a corresponding function neme, and

(3) initialization means actuated upon each iinitial application of electric power to said function module, said initialization means including (a) means for requesting information bus control upon initialization, (b) means for reading said initialization counter upon obtaining control of said information bus, (c) means for determining whether said initialization counter is in said predetermined initialization count upon said reading, (d) means for initializing said global function table and setting said initialization counter to "1" if said initialization counter is in said predetermined initialization count, (e) means for incrementing said initialization counter if said initialization counter is not in said predetermined initialization count, (f) means for assigning an information bus access address for said function module correspondng to the current count of said initialization counter, (g) means for transmitting via said information bus said information bus access address to said logical arbiter memory means for storage in said global function table said function name of said computational function, (h) means for releasing control of said information bus after transmitting said information bus access address to said global function table, and (i) means for executing a delay for a predetermined period of time after releasing control of said information bus, thereby permitting initialization by other function modules having lower bus priority; and

a bus arbitration means connected to said information bus and each of said function modules for permitting one and only one function module to control data transfer via said information bus based upon said bus priority of any function module requesting control of said information bus.

6. A data processing system as claimed in claim 5 wherein:

at least one function module includes means for requesting a computational function from another module by accessing said global function table via said information bus for recalling from said global function table the information bus access address of a function name corresponding to the desired computational function and transmitting a function request via said information bus to said recalled information bus access address.

7. A data processing system comprising:

an information bus for transferring data;

a logical arbiter memory means connected for transfer of data to and from said information bus, having an information bus access address designating means for assigning information bus access addresses by assigning successive module numbers upon each initial application of electric power to said logical arbiter memory means, a global function table for storing therein function names together with their corresponding information bus access address, and a function address means for transmitting said information bus access address corresponding to a function name in response to a function address request on said information bus;

a plurality of function modules each connected for transfer of data to and from said information bus in response to function requests, each function module having

(1) a bus priority for determining priority of control of dataa transfer via said information bus,

(2) function means to perform a computational function in response to a corresponding function request on said information bus directed to a corresponding information bus access address designated by said information bus access address designation means, said computational function having a corresponding function name, and

(3) initialization means actuated upon each initial application of electric power to said function module, said initialization means including (a) means for requesting information bus control upon initialization, (b) means for transmitting via said information bus said function name of said computational function to said logical arbiter memory means for storage in said global function table upon obtaining control of said information bus, (c) means for releasing control of said information bus after transmitting said function name to said global function table, and (d) means for executing a delay for a predetermined period of time after releasing control of said information bus, thereby permitting initialization by other function modules having lower bus priority, and

a bus arbitration means connected to said information bus and each of said function modules for permitting one and only one function module to control data transfer via said information bus based upon said priority of any function module requesting control of said information bus.

8. A data processing system as claimed in claim 7 wherein:

at least one function module includes means for requesting a computational function from another module by accessing said global function table via said information bus for recalling from said global function table the information bus access address of a function name corresponding to the desired computational function and transmitting a function request via said information bus to said recalled information bus access address.