Stacked semiconductor memory

• US 4,633,438 A
• Filed: 12/13/1984
• Issued: 12/30/1986
• Est. Priority Date: 12/19/1983
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited (Hitachi, Ltd.)
• Inventors: Kume, Hitoshi, Kaga, Toru, Horiuchi, Masatada, Hagiwara, Takaaki, Shimizu, Akihiro, Igura, Yasuo
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/681,027
• Time in Patent Office: 747 Days
• Field of Search: 365/187, 365/182, 365/51, 307/304, 357/23.7
• US Class Current: 365/51
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.

A memory cell capable of extremely large scale integration can be obtained.

Claims

1. A semiconductor memory comprising:

a first transistor for writing, said first transistor having a gate electrode, and source and drain regions;

a second transistor for amplifying, said second transistor having a gate electrode, and source and drain regions; and

a third transistor for reading, said third transistor having a gate electrode, and source and drain regions,

wherein said drain or source of said first transistor is connected to said gate electrode of said second transistor,

wherein said drain or source of said second transistor is connected to said source or drain of said third transistor, and

wherein at least a part of said first transistor is stacked on said third transistor in such a manner that an insulating film is formed on said gate electrode of said third transistor and said first transistor is stacked over said insulating layer.

2. A semiconductor memory as set forth in claim 1, wherein said drain or source of said first transistor is connected to said gate electrode of said second transistor by a semiconductor layer disposed by the same production step of forming the gate electrode and the drain or source region.

3. A semiconductor memory as set forth in claim 1, wherein said gate electrode of said second transistor and said gate electrode of said third transistor are disposed by the same production step.

4. A semiconductor memory as set forth in claim 2, wherein a region formed by connecting the source or drain of said first transistor to said source or drain of said third transistor is used as a data input/output portion, and said source of drain of said second transistor is connected to a reference potential.

5. A semiconductor memory as set forth in claim 3, wherein a region formed by connecting the source or drain of said first transistor to said source or drain of said third transistor is used as a data input/output portion, and the source or drain of said second transistor is connected to a reference potential.

6. A semiconductor memory including:

a semiconductor substrate;

a first region used as a source region or a drain region, a second region used as a drain region and a source region, and a third region used as a drain region or a source region on one major surface of said substrate;

a first insulating film formed on said surface of said substrate between at least said first and second regions;

a first electrode formed on said first insulating film;

a second insulating film formed on said surface of said substrate between at least said second region and said third region;

a second electrode formed on said second insulating film;

a third insulating film formed on said first electrode and extending from an area above said first region to an area above said second region;

a semiconductor layer formed over said third insulating film, one edge of said semiconductor layer electrically being connected to said first region and the other edge of said semiconductor layer electrically being connected to said second electrode;

a fourth insulating film formed on a part of said semiconductor layer; and

a third electrode formed on said fourth insulating film.

7. A semiconductor memory as set forth in claim 6, wherein said second electrode and said semiconductor layer are disposed by the same production step and are a continuous layer.

8. A semiconductor memory as set forth in claim 6, wherein said first insulating film and said second insulating film are a continuous insulating film over said second region.

9. A semiconductor memory as set forth in claim 6, wherein said first electrode and said second electrode are disposed by the same production step.

10. A semiconductor memory as set forth in claim 6, wherein said first region, said second region, said first insulating film and said first electrode form a reading transistor of a three-transistor memory cell, wherein said second region, said third region, said second insulating film and said second electrode form an amplifying transistor of said three-transistor memory cell and wherein said semiconductor layer includes regions to form a source and a drain separated from one another by a portion of said semiconductor layer formed under said fourth insulating layer so that said source and drain regions of said semiconductor layer, said fourth insulating film and said third electrode form a writing transistor of said three-transistor memory cell.