Cluster computer based education delivery system

• US 4,636,174 A
• Filed: 11/17/1983
• Issued: 01/13/1987
• Est. Priority Date: 11/17/1983
• Status: Expired due to Fees

• Current Assignee: University of Illinois
• Original Assignee: University of Illinois
• Inventors: Andersen, David M., Rader, Robert K., Sherwood, Bruce A., Tucker, Paul T., Bitzer, Donald L.
• Primary Examiner(s): Picard, Leo P.
• Application Number:
  US06/552,947
• Time in Patent Office: 1,153 Days
• Field of Search: 273/85 G, 273/237, 434/323, 434/335
• US Class Current: 434/335
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G09B 7/04 characterised by modifying the teaching programme in response to a wrong answer, e.g. repeating the question, supplying a further explanation

Abstract

An improved computer based education system maintains rapid response to user input without limits to the number of stations. The system incorporates a dedicated processor at each user station so that the user station receives executable code as opposed to a display map. To support plural users a cluster subsystem is provided interconnected to the user stations via a high speed bidirectional communication subsystem. The cluster also includes a mass storage device, a high speed buffer, communications interface and at least one processor for serving user requests.

Claims

1. An interactive instructional multi-processor system for providing instructional programs for execution at one or more processor stations while relieving memory requirements at said processor stations without allowing a perceivable delay to users at said processor stations as a result of paging of instructional program segments, comprising:

a cluster subsystem and a plurality of processor stations interconnected by a high speed multi-access communication subsystem, in which said cluster subsystem comprises;

at least one mass storage device for storing a library of instructional programs averaging at least about 50 kilobytes in length,

high speed buffer means coupled to said mass storage device for simultaneously storing a plurality of instructional programs,

an interface for said speed communication sub-system, and

processor means including a digital processor for managing said mass storage device, said high speed buffer means and said interface, said processor means further including a bus interconnecting said mass storage device, said high speed buffer means, said interface and said digtal processor, said digital processing including controller means for transferring a requested instructional program from said mass storage device to said high speed buffer means and for retaining said instructional program in said high speed buffer means for at least a target time related to the plurality of processor stations coupled to said cluster subsystem,

each of said processor stations comprising;

a microprocessor, electronic memory of about 64 Kbytes or less and display controlled by said microprocessor,

an interface for bidirectional communication coupled to and controlled by said microprocessor and coupled to said high speed communication subsystem,

said high speed communication subsystem including means for supporting high speed bidirectional communication between said cluster subsystem and a plurality of said processor stations at a rate of at least one megabit per second,

whereby said electronic memory at said microprocessor need not have a capacity to store an entire instructional program, rather a microprocessor can execute one of said instructional programs in segments without noticeable delay in loading an instructional program segment from said high speed buffer means for execution.

2. The system of claim 1 in which said communication subsystem includes means for packetizing and transmitting messages form said cluster subsystem to said processor stations and from said processor stations to said cluster subsystem.

3. The system of claim 1 in which said at least one mass storage device is characterized by an access rate of at least twenty accesses per second and a transfer rate of at least 500 kilobytes per second.

4. The system of claim 3 in which the transfer rate of said mass storage device is at least one megabyte per second.

5. The system of claim 1 in which capacity of said electronic memory and high speed buffer means are selected to be complementary so that as high speed buffer memory capacity is increased, electronic memory capacity is decreased and vice versa.

6. The system of claim 1 which includes a communication link extending between said cluster subsystem and a central computer for the transfer of student data.

7. The system of claim 1 which includes a further interactive instructional multi-processor system and a communication link extending between said interactive instructional multi-processor system.

8. A method of providing interactive instructional programs at one of a plurality of processor stations comprising the steps of:

(a) providing a mass storage device for storing a number of instructional programs for execution at said processor stations,

(b) providing a high speed buffer memory of capacity sufficient to simultaneously store a plurality of said instructional programs,

(c) providing a plurality of processor stations for executing segments of an instructional program in response to a user request,

(d) providing a multi-access communication sub-system interconnecting said plurality of processor stations and said high speed buffer memory,

(e) formulating a request for a specific program segment, at a processor station, in response to a user input, and communicating said request to said cluster subsystem via said mult-accoss communication sub-system,

(f) responding at said cluster subsystem by extracting the requested program segment from said high speed buffer memory and transmitting said program segment to said requesting processor station via said multi-access communication sub-system.