Vertical Schottky barrier gate field-effect transistor in GaAs/GaAlAs

• US 4,636,823 A
• Filed: 06/05/1984
• Issued: 01/13/1987
• Est. Priority Date: 06/05/1984
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Margalit, Shlomo, Rav-Noy, Zeev, Yariv, Amnon
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/617,495
• Time in Patent Office: 952 Days
• Field of Search: 357/23.3, 357/23.4, 357/23.2, 357/15, 357/16, 357/22, 357/55
• US Class Current: 257/192
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722

Abstract

High transconductance vertical FETs are produced in III-V epitaxially grown layers doped n, p and n, with the in-between submicron (0.15 μm) layer serving as the FET channel. The layer on the drain side of the channel may be thicker (3 μm) than on the source side (1.5 μm). The structure is V-grooved to expose a nearly vertical surface that is Si implanted or regrown with graded n-type GaAs/GaAlAs before a gate contact is deposited on the vertical structure. An alternative to employ a heterostructure with GaAlAs layers for the source and drain, and GaAs for the channel layer. Graded GaAs/GaAlAs is then selectively regrown in the channel layer.

Claims

1. A vertical field-effect transistor comprised of epitaxial layers of III-V semiconductor material including a drain layer grown more than one micron thick, a channel layer, and a source layer grown more than one micron thick, with said channel layer grown between said source and drain layers to a controlled submicron thickness for high transconductance of the transistor, and have exposed a cross sectional surface through said channel layer,and further including source and drain contacts for respective one of said source and drain layers, and means for providing a depletion layer of a Schottky barrier gate on the exposed cross sectional surface of said submicron channel layer.

2. A vertical field-effect transistor as defined in claim 1 wherein said source and drain layers are n-type GaAs layers, and said channel layer is p-type GaAs.

3. A vertical field-effect transistor as defined in claim 1 wherein said three epitaxial layers are grown on a GaAs substrate with a GaAs channel layer between said source and drain layers, and said means is comprised of silicon implanted in said channel layer through said exposed vertical surface to provide the depletion layer of a Schottky barrier gate on the channel layer, whereby modulation of the depletion region in the channel layer with a signal applied on said gate will control conduction between said source and drain contacts.

4. A vertical field-effect transistor as defined in claim 1 wherein said three epitaxial layers are grown on n+GaAs substrate with a p-type GaAs channel layer in between n-type GaAs source and drain layers, and said means is comprised of graded n-type GaAs/GaAlAs regrown on said exposed cross sectional surface to provide the depletion layer of a Schottky barrier gate on the p-type channel layer.

5. A vertical field-effect transistor as defined in claim 1 wherein said three epitaxial layers are grown on n⁺ GaAs substrate with a p-type GaAs channel layer in between n-type Ga_1-x Al_x As source and drain layers, and said means is comprised of n-type graded GaAs/GaAlAs preferentially regrown on the exposed cross sectional surface of said p-type channel layer to provide the depletion layer of a Schottky barrier gate on the p-type channel layer.

6. A vertical field-effect transistor as defined in claim 3 wherein said source and drain layers are n-type GaAs layers, and said channel layer is p-type GaAs.

7. A high transconductance vertical field-effect transistor comprising epitaxially grown layers of GaAs semiconductor material grown on a substrate of said material doped n⁺, a first thick layer of about 3 μ

m in thickness of said material n doped about 1.5×

10¹⁷ cm^-3, a second thin layer about 0.15 μ

m in thickness of said material p doped from 1 to 2×

10¹⁷ cm^-3, and a third layer about 1.5 μ

m in thickness of said material n doped about 3×

10¹⁷ cm^-3, a groove of about 2.5 μ

m depth to expose in a cross sectional surface said second thin layer, source and drain contacts for respective ones of said third layer and substrate, and means for providing a depletion region of a Schottky barrier gate on said exposed cross sectional surface of said second, thin layer.

8. A vertical field-effect transistor as defined in claim 7 wherein said means is comprised of silicon implanted in said thin, second layer through said exposed cross sectional surface to provide the depletion layer of a Schottky barrier gate, and a metal contact deposited over said implanted silicon.

9. A vertical field-effect transistor as defined in claim 7 wherein said means is comprised of graded n-type GaAs/GaAlAs grown over said exposed cross sectional surface to provide the depletion layer of a Schottky barrier gate, and a metal contact deposited over said graded GaAs/GaAlAs.

10. A high transconductance vertical field-effect transistor comprising epitaxially grown layers of GaAs and GaAlAs semiconductor materials grown on a substrate of said n+GaAs, a first thick layer about 3 μ

m in thickness of GaAlAs n doped about 1.5×

10¹⁷ cm^-3, a second, thin layer about 0.15 μ

m in thickness of GaAs p doped from 1 to 2×

10¹⁷ cm^-3, and a third layer about 1.5 μ

m in thickness of GaAlAs material in doped about 3×

10¹⁷ cm^-3 ;

a groove of about 2.5 μ

m depth to expose a cross sectional surface of said second layer, source and drain contacts for respective ones of said third layer and substrate, and means for providing a Schottky barrier gate in the exposed cross sectional surface of said second layer comprised of graded n-type GaAs/GaAlAs selectively regrown over the exposed cross sectional surface of said second layer in said groove and a metal contact deposited over said graded GaAs/GaAlAs selectively regrown.