Extracting digital data from a bus and multiplexing it with a video signal
First Claim
1. Apparatus for monitoring a data bus, selecting data from the bus, encoding the data, and multiplexing the encoded data with a video signal from a separate video source;
- the data bus being a device addressable multiplex serial digital data bus having a plurality of devices coupled thereto, each device having a unique device address field included in messages which it sends via the data bus;
said apparatus comprising;
apparatus bus means having coupled thereto CPU means, programmable memory means, random access memory means, bus decoder means, and video encoder means, the bus decoder means being also coupled to said data bus;
wherein the video encoder means comprises video logic means coupled between said video source and a video output, the video logic means being also coupled to the apparatus bus means;
wherein the apparatus includes means for performing actual data acquisition from the data bus as a passive function with programmable data selection under control of the CPU means, using the device address fields, the bus decoder means including means for receiving data from the data bus and performing preprocessing of messages, means to time-tag data messages, and to assemble data messages into a message block buffer;
wherein the video encoder means includes means for synchronizing an internal video timing generator to the video signal from the video source, and means for receiving selected data messages from the message block buffer, means for formatting and encoding the messages as encoded data signals, and insertion of encoded data signals into the video signal for output to said video output.
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Abstract
A television video data instrumentation recording system is coupled to a Bus Monitor/Video Encoder to incorporate a digital data recording capability within the normal video signal recording process while allowing for later digital data recovery during video playback. The digital data is acquired from a device addressable serial data bus which is normally an asynchronously polled system for exchanging data messages between a bus master device and multiple slave devices where each slave device has a unique device identification code for its messages. Data acquisition is a passive function (relative to the data bus) involving the hardward programmable selection of messages of interest (based on the message device code) and the software programmable deletion of messages that contain no data of interest. Another feature of data acquisition is that a time reference for time-of-acquisition is appended to the acquired messages of interest. This approach also intercepts the video signal between the television source and the recording system, programmably assembles the acquired data messages into recording data blocks synchronized to the video signal, and performs a formatted serial encoding conversion of the data blocks into a video signal. Once recorded, the video signal can be played back with programmably selected portions of the video subjected to a decoding conversion that recovers the formatting information and data such that the original acquired data messages (and time tag) can be reconstructed with minimum data loss due to recovery errors.
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Citations
5 Claims
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1. Apparatus for monitoring a data bus, selecting data from the bus, encoding the data, and multiplexing the encoded data with a video signal from a separate video source;
- the data bus being a device addressable multiplex serial digital data bus having a plurality of devices coupled thereto, each device having a unique device address field included in messages which it sends via the data bus;
said apparatus comprising;apparatus bus means having coupled thereto CPU means, programmable memory means, random access memory means, bus decoder means, and video encoder means, the bus decoder means being also coupled to said data bus; wherein the video encoder means comprises video logic means coupled between said video source and a video output, the video logic means being also coupled to the apparatus bus means; wherein the apparatus includes means for performing actual data acquisition from the data bus as a passive function with programmable data selection under control of the CPU means, using the device address fields, the bus decoder means including means for receiving data from the data bus and performing preprocessing of messages, means to time-tag data messages, and to assemble data messages into a message block buffer; wherein the video encoder means includes means for synchronizing an internal video timing generator to the video signal from the video source, and means for receiving selected data messages from the message block buffer, means for formatting and encoding the messages as encoded data signals, and insertion of encoded data signals into the video signal for output to said video output. - View Dependent Claims (2)
- the data bus being a device addressable multiplex serial digital data bus having a plurality of devices coupled thereto, each device having a unique device address field included in messages which it sends via the data bus;
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3. Apparatus for monitoring a data bus, selecting data from the bus, encoding the data, and multiplexing the encoded data with a video signal from a separate video source;
- the data bus being a device addressable multiplex serial digital data bus having a plurality of devices coupled thereto, each device having a device address, to send messages with a serial data word transmission sequence including message control words having the device addresses and message data words;
said apparatus comprising;a bus monitor subassembly and a video encoder subassembly; wherein the bus monitor subassembly comprises a main bus, a monitor bus, a main CPU coupled to the main bus, a monitor CPU coupled to the monitor bus, bus decoder means coupled between said data bus and the monitor bus, the bus decoder means including bus decoder control circuitry, a monitor interface coupled between the main bus and the monitor bus, the monitor interface being also coupled to the monitor CPU, first memory means coupled to both the monitor bus and the main bus, said first memory means including a programmer which comprises programmable read only memory means coupled to the main bus, and second memory means comprising random access memory coupled to the main bus; wherein the video encoder subassembly comprises an encoder bus coupled via video encoder interface means to the main bus, video logic means coupled between said video source and a video output, the video logic means being also coupled to the encoder bus, video locking and control circuits coupled to the encoder bus and also to the video logic means, encoder control means coupled to the encoder bus, formatter encoder means coupled to the encoder bus and also to the video logic means, and data control means coupled to the encoder bus; wherein the main CPU has over-ride mode-control means and access means to the monitor CPU and the monitor bus, the main and monitor CPUs have program interrupt cross-linkage means and also share said first memory means, the main CPU having means to use the first memory means to provide the monitor CPU with task programs and to access acquired data, the main CPU includes means for using said programmer for permanent entry of monitor CPU subroutine programs; wherein the main CPU includes means under software control for performing tasks, including (a) means operating in real time for gaining and holding synchronization with said video signal from the video source via video locking and control functions of the video encoder subassembly via the main bus, (b) means operating in real time for oversight of bus-monitor subassembly operations and the interchange of empty and full data buffers for acquired message data blocks, (c) means operating in real time for synchronization and queuing of full message data blocks from the data bus, and (d) means for exception handling and error recovery for the bus monitor and video encoder; wherein the bus monitor subassembly includes means for performing actual data acquisition from the data bus under direct control of the monitor CPU, using the device addresses, the bus decoder means including means for receiving data from the data bus and performing message grouping of the serial data word transmission sequence, with means effective as each message is received for testing the device address of the control words against a programmable look-up table to identify message treatment, and means based on end-of message for the monitor CPU to delete non-data messages, to time-tag data messages, and to assemble data messages into a message block buffer supplied by the main CPU; wherein the video-encoder subassembly includes means for synchronizing an internal video timing generator to the video signal from the video source, and means for the generation and insertion of encoded data signals into the video signal for output to said video output. - View Dependent Claims (4, 5)
- the data bus being a device addressable multiplex serial digital data bus having a plurality of devices coupled thereto, each device having a device address, to send messages with a serial data word transmission sequence including message control words having the device addresses and message data words;
Specification