Method and apparatus for monitoring automated testing of electronic circuits

• US 4,637,020 A
• Filed: 05/17/1984
• Issued: 01/13/1987
• Est. Priority Date: 08/01/1983
• Status: Expired due to Fees

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Schinabeck, John
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US06/611,449
• Time in Patent Office: 971 Days
• Field of Search: 371/20, 371/25, 371/27, 324/73 R, 324/73 AT, 324/73 PC, 364/579, 364/580
• US Class Current: 714/736
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/3191 Calibration
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: H03K 2005/00247 using counters
• CPC Class Codes: H03K 2005/00254 using microprocessors
• CPC Class Codes: H03K 2005/0026 using memories or FIFO's
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence

Abstract

A plurality of signal applying and monitoring circuits are coupled to pins of an electronic device being tested to force test stimuli signals representing logic states or other parameters onto input pins of the device under test. The responses to the stimuli signals are monitored while the device is being tested. Each signal applying and monitoring circuit includes a node to be coupled to a pin of the device under test, a device power supply connected to the node for supplying a test bias signal, a comparison circuit connected to the node for indicating the relative magnitude of the test bias signal with respect to the bias level at the node, and a latch circuit responsive to the output signal produced by the comparison circuit. The device power supply is included for providing test bias signals to test power drain during functional testing. The transitions of the device power supply are monitored and latched for providing a record of the power drain of the device being tested. Other features are also disclosed.

Claims

1. A method for continuously applying and monitoring a test bias signal at a node of a device under test including digitally programmed source means having a preselected programmed voltage-current characteristic defined by not-to-exceed voltage rail and current rail levels for supplying a test bias signal to the node, comparison means connected to the node, and means for latching the output signal produced by the comparison means, the method comprising the steps of:

connecting the test bias signal to the node;

continuously comparing the voltage applied to the node with the preselected programmed voltage rail level;

providing an indication of the relative magnitude of the voltage applied to the node with respect to the voltage rail level;

setting first latching means when the voltage applied to the node reaches the voltage rail level;

continuously comparing the current at the node with the preselected programmed current rail level;

providing an indication of the relative magnitude of the current at the node with respect to the current rail level; and

setting second latching means when the current at the node reaches the current rail level.

2. The method of claim 1, further comprising the steps of:

continuously comparing the test bias signal voltage applied to the node with a reference voltage for determining the polarity of the test bias signal voltage;

continuously comparing the test bias signal current at the node with a reference current for determining the polarity of the test bias signal current;

setting third latching means when the test bias signal voltage applied to the node is positive and the test bias signal current at the node is positive;

setting fourth latching means when the test bias signal voltage applied to the node is positive and the test bias signal current at the node is negative;

setting fifth latching means when the test bias signal voltage applied to the node is negative and the test bias signal current at the node is negative; and

setting sixth latching means when the test bias signal voltage applied to the node is negative and the test bias signal current at the node is positive.

3. The method of claim 2, further comprising the steps of:

continuously comparing the test bias signal with the bias level at the node;

providing an indication of the relative magnitude of the test bias signal with respect to the bias level; and

setting another latching means when the test bias signal has a predetermined relationship with respect to the bias level.

4. The method of claim 3, further comprising the steps of:

continuously comparing the bias level voltage at the node with a Kelvin reference voltage;

providing an indication of the relative magnitude of the bias level voltage at the node with respect to the Kelvin reference voltage; and

setting an additional latching means when the bias level voltage at the node has a predetermined relationship with respect to the Kelvin reference voltage.

5. The method of claim 1 wherein the test bias signal is a forcing function which starts at zero volts and one percent of the maximum current of a preselected voltage-current range.

6. Apparatus for continuously applying and monitoring a test bias signal to a node of a device under test, comprising:

digitally programmed source means connected to the node, the digitally programmed source means having a preselected programmed voltage-current characteristic defined by not-to-exceed voltage rail and current rail levels for supplying test bias signals to the node;

first comparison means connected to the node for continuously comparing the voltage applied to the node with the preselected programmed voltage rail level;

first latching means for providing an indication when the voltage applied to the node reaches the voltage rail level;

second comparison means connected to the node for continuously comparing the current at the node with the preselected programmed current rail level; and

second latching means for providing an indication when the current at the node reaches the current rail level.

7. Apparatus as in claim 6, further comprising:

third comparison means for continuously comparing the test bias signal voltage applied to the node with a reference voltage for determining the polarity of the test bias signal voltage;

fourth comparison means for continuously comparing the test bias signal current at the node with a reference current for determining the polarity of the test bias signal current;

third latching means for providing an indication when the test bias signal voltage applied to the node is positive and the test bias signal current at the node is negative;

fourth latching means for providing an indication when the test bias signal voltage applied to the node is positive and the test bias signal current at the node is negative;

9. Apparatus as in claim 7, further comprising:

fifth comparison means connected to the node for continuously indicating the relative magnitude of the test bias signal with respect to the bias level at the node; and

another latching means for providing an indication when the test bias signal has a predetermined relationship with respect to the bias level.

11. Apparatus as in claim 9 wherein the digitally programmed source means is a crossover source.

8. fifth latching means for providing an indication when the test bias signal voltage applied to the node is negative and the test bias signal current at the node is negative;

and

sixth latching means for providing an indication when the test bias signal voltage applied to the node is negative and the test bias signal current at the node is positive.

10. Apparatus as in claim 8, further comprising:

sixth comparison means for continuously comparing the bias level voltage at the node with a Kelvin reference voltage; and

an additional latching means for providing an indication when the bias level voltage at the node has a predetermined relationship with respect to the Kelvin reference voltage.

12. Apparatus as in claim 10 wherein the digitally programmed source means supplies a test bias signal in the form of a forcing function that starts at zero volts and one percent of the maximum current of a preselected voltage-current range.