CMOS bias voltage generating circuit

• US 4,638,184 A
• Filed: 09/13/1984
• Issued: 01/20/1987
• Est. Priority Date: 09/22/1983
• Status: Expired due to Term

• Current Assignee: OKI Electric Industry Company Limited
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Kimura, Kikuo
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US06/650,408
• Time in Patent Office: 859 Days
• Field of Search: 323/282, 323/286, 323/311, 363/19-21, 307/265, 307/296 R, 307/297
• US Class Current: 327/541
• CPC Class Codes: G05F 1/465 Internal voltage generators for integrated circuits, e.g. step down generators

Abstract

A bias generating circuit for reducing an external DC power supply voltage to a predetermined, lower, stable DC voltage used as a power source for internal logic circuits in a semiconductor IC chip includes an oscillator for converting the external DC voltage into a pulse signal, a smoothing circuit for converting a pulse signal into the lower DC voltage, and a control circuit interposed between the oscillator and the smoothing circuit for varying the pulse duration of the pulse signal from the oscillator to a changed pulse signal, and for regulating the lower DC voltage to a predetermined amplitude in response to the voltage variation in the lower DC voltage. The control circuit comprises a CMOS inverter, a CMOS buffer circuit for varying the pulse duration of the output signal of the CMOS inverter, and a voltage compensating circuit for controlling the transconductance of the CMOS inverter in response to the variation of the lower DC voltage.

Claims

1. A CMOS bias voltage generating circuit for use in a semiconductor integrated circuit device and for reducing an external DC power supply voltage to a lower DC bias voltage, comprising:

oscillating means coupled to said external DC power supply for converting said external voltage into a first clock pulse signal;

smoothing circuit means for converting a second clock pulse signal into said lower DC bias voltage;

CMOS inverter means for inverting said first clock pulse signal from said oscillating means;

CMOS buffer means for varying the pulse duration of the output signal from said CMOS inverter means to output said second clock pulse signal to said smoothing circuit means; and

voltage compensating means for varying the transconductance of said CMOS inverter means in response to a variation of said lower DC bias voltage to regulate the pulse duration of said first clock pulse signal to thereby regulate said lower DC bias voltage to a predetermined amplitude.

2. The circuit of claim 1, wherein said voltage compensating means comprises P and N-type MOS transistors connected to said CMOS inverter means, respectively.

3. The circuit of claim 2, wherein said CMOS buffer means comprises a plurality of CMOS inverters serially connected to one another, said oscillating means comprises a CMOS ring oscillator, and said smoothing circuit means comprises a capacitor.

4. A CMOS bias voltage generating circuit for use in a semiconductor integrated circuit device and for reducing an external DC power supply voltage to a lower DC bias voltage, comprising:

oscillating means coupled to said external DC power supply for converting said external voltage into a first clock pulse signal;

smoothing circuit means for converting a second clock pulse signal into said lower DC bias voltage;

CMOS buffer means for varying the pulse duration of said first clock pulse signal from said oscillating means to output said second clock pulse signal;

CMOS inverter means for inverting said second clock pulse signal from said CMOS buffer means; and

voltage compensating means for varying the transconductance of said CMOS inverter means in response to a variation of said lower DC bias voltage to regulate the pulse duration of said second clock pulse signal to thereby regulate said lower DC bias voltage to a predetermined amplitude.

5. The circuit of claim 4, wherein said voltage compensating means comprises P and N-type MOS transistors connected to said CMOS inverter means, respectively.

6. A circuit as claimed in claim 5, wherein said CMOS buffer means comprises a plurality of CMOS inverters serially connected to one another, said oscillating means comprises a CMOS ring oscillator, and said smoothing circuit means comprises a capacitor.