Digital-analog converter

• US 4,638,303 A
• Filed: 10/28/1985
• Issued: 01/20/1987
• Est. Priority Date: 09/07/1982
• Status: Expired due to Term

• Current Assignee: Toshiba Corporation
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Sakamoto, Shigemi, Masuda, Eiji
• Primary Examiner(s): Sloyan, T. J.
• Application Number:
  US06/792,181
• Time in Patent Office: 449 Days
• Field of Search: 340/347 DA, 340/347 M, 340/347 CC
• US Class Current: 341/136
• CPC Class Codes: H03M 1/682 both converters being of the unary decoded type
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals

Abstract

A digital-analog converter wherein reference voltage is divided by a first string-like resistor array, whose two adjacent outputs are selected by a first switch array depending upon the contents of upper bits of a digital signal and applied to the both ends of a second string-like resistor array, and one of switches in a second switch array is selectively turned on responsive to the contents of lower bits of said digital signal to pick up one of the divided voltages of said second resistor array.

Claims

1. A digital analog converter, coupled to a reference voltage, for receiving a multi-bit digital signal and producing an analog value, said converter comprising:

a first resistor array consisting of a plurality of resistors connected in series to divide said reference voltage into M output voltages, where M is a positive integer;

a first switch array for receiving said output voltages of said first resistor array to select two adjacent ones of said output voltages in accordance with a first number of upper bits of said digital signal;

a first select switch for outputting one of said two adjacent output voltages selected by said first switch array;

a second select switch for outputting the other of said two adjacent output voltages selected by said first switch array;

two buffer amplifiers, coupled to said select switches, each receiving a different one of the two selected output voltages from said select switches in accordance with the states of said first and second select switches;

a second resistor array consisting of a plurality of resistors connected in series to receive said output voltages from said buffer amplifiers and divide said output voltages into N voltages, where N is a positive integer;

a second switch array for selecting one of said output voltages from said second resistor array in accordance with the contents of a second number of lower bits of said digital signal;

an averaging circuit including means for receiving the selected output voltage from the second switch array and obtaining an average of said selected output voltage; and

an alternating controller for synchronously controlling said select switches and said averaging circuit.

2. A digital-analog converter according to claim 1 further including an intermediate resistor array, an intermediate switch array and an intermediate decoder,

wherein said intermediate resistor array includes means for receiving first ones of said divided voltages from said first switch array, said first divided voltages being applied to both ends of said intermediate switch array,

wherein said intermediate switch array includes means for selecting two adjacent ones of said divided voltages from said intermediate resistor array, and

wherein said intermediate decoder includes means for controlling said intermediate switch array to code convert a third number of intermediate bits of said digital signal between said upper and lower bits in response to the lowest order bit of said upper bits which is applied to the intermediate decoder to cause the intermediate switch array to select two adjacent divided voltages from said intermediate resistor array and apply them to the second resistor array.

3. A digital-analog converter according to claim 1, wherein said first resistor array comprises resistors having an equal resistor value and connected in series with one another.

4. A digital-analog converter according to claim 1, wherein said second resistor array comprises resistors, all but two of which are equal in resistor value, connected in series with one another, and the other two resistors of said second resistor array having a value half of that of the other of said resistors in said second resistor array, said other two resistors each being connected in series to a different end of said second resistor array.

5. A digital-analog converter according to claim 1, wherein said first switch array comprises first and second array switches, said first array switches each receiving at one switch end the odd-numbered divided voltages of said first resistor array and being connected to one another at the other switch end, and said second array switches each receiving at one switch end the even-numbered divided voltages of said first resistor array and being connected to one another at the other switch end.

6. A digital-analog converter according to claim 1, wherein said first and second switch arrays employ analog switches provided with MOS FETs.

7. A digital-analog converter according to claim 1,

wherein said first switch array includes means for selecting the two output voltages in accordance with the changes in the upper bits of the digital signal such that when the value represented by the upper bits increases by a minimum unit, the higher of said output voltages selected is kept selected and an output voltage higher than and adjacent to the higher output voltage selected is newly selected, and when the value represented by the upper bits decreases by the minimum unit, the lower of said output voltages selected is kept selected and an output voltage lower than and adjacent to the lower voltage selected is newly selected, and

wherein said second switch array includes means for selecting one of said divided voltages in accordance with the lower bits of the digital signal and the least significant bit of the upper bits of the digital signal.

8. A digital-analog converter according to claim 1, further comprising shift registers and latches, and

wherein the digital signal which is to be converted to an analog signal is applied in series to said shift register whose outputs are transferred in parallel to said latches.