Data entry interface assembly

• US 4,638,422 A
• Filed: 05/18/1984
• Issued: 01/20/1987
• Est. Priority Date: 05/19/1983
• Status: Expired due to Fees

• Current Assignee: Elwyn Rees
• Original Assignee: Elwyn Rees
• Inventors: Rees, Elwyn
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/611,981
• Time in Patent Office: 977 Days
• Field of Search: 364/200 MS File
• US Class Current: 710/55
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An interface assembly enables a number of remote data entry terminals to transmit information to a computer. The interface assembly 30 comprises a memory buffer 42 comprising one byte of memory for each terminal 32. The terminals 32 are hard-wired to individual memory addresses, so that each byte of the memory is driven to the value dictated by the user'"'"'s last input at its respective terminal. An address generator 44 repeatedly scans the memory buffer 42, transmits to an interface 50, 52 or 54 information identifying the address and the byte value held at that address and resets the address to a null value. In this way the input information is transmitted byte by byte to the CPU through the same interface which is chosen for its handshake compatibility with the CPU. If desired plural interfaces may be provided in the assembly, so that the CPU may simply be plugged into that one which is compatible.

Claims

1. An interface assembly enabling a central processing unit to accept and allocate information from a number of remote data entry terminals, which assembly comprises:

an interface to match the interface convention at an i/o port of the central processing unit;

a memory buffer comprising one byte of memory for each of the remote data entry terminals to be served;

means for supplying data from the said remote data entry terminals to individually assigned bytes of the memory buffer;

an address generator for addressing individual bytes of the said memory buffer in sequence;

means for transferring to the said interface information identifying each individual byte address and the value held by the byte at each said address;

and means for resetting the value of each byte addressed to a null value on such transfer.

2. An interface assembly according to claim 1, comprising two or more of the said interfaces having mutually different interface conventions, enabling the assembly to match the interface conventions of different central processing units with which it might be used.

3. An interface assembly according to claim 2, wherein the interfaces comprise one parallel and one serial interface.

4. An interface assembly according to claim 3, wherein three or more interfaces are provided, including one which has a user-definable convention.

5. An interface assembly according to claim 2, 3 or 4, wherein the means for transferring the information supplies the necessary address and byte value information to both or all interfaces simultaneously.

6. An interface assembly according to claim 2, 3, or 4, wherein the means for transferring the information supplies the necessary address and byte value information to an interface selector which transmits the information to a preselected interface chosen for its compatibility with the central processing unit.

7. An interface assembly according to claim 1, wherein the address generator is arranged to be driven in response to an output of the central processing unit.