Virtual memory address translation mechanism with controlled data persistence

• US 4,638,426 A
• Filed: 09/19/1983
• Issued: 01/20/1987
• Est. Priority Date: 12/30/1982
• Status: Expired

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mergen, Mark F., Chang, Albert, Radin, George, Cocke, John
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/573,975
• Time in Patent Office: 1,219 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/216
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0781 Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means
• CPC Class Codes: G06F 2212/683 Invalidation

Abstract

A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step. To greatly enhance the translation of frequently used virtual addresses, a special set of translation tables referred to herein as a Translation Look-Aside, Buffer (TLB) contain current effective to real address translations for use where frequently referenced addresses are requested. The TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB is examined for a match with the effective address. If the addresses match a successful address translation is possible and the real address stored in the address field of the TLB is available for system use. If the desired effective address is not present in the TLB, the page frame tables stored in main memory are accessed and searched for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.

Claims

1. A method for converting virtual memory addresses supplied by an associated central processing unit into real memory addresses within a large hierarachical memory system wherein the virtual memory address space is significantly larger than the actual memory which method comprises;

the CPU generating a first virtual address comprising a segment identifier field, a page offset field, and a byte offset field,

utilizing the segment identifier field to access a set of segment registers pointed to by the segment identifier field,

accessing the contents of the addressed segment register and concatenating the contents of same with the page offset and byte offset fields of said first virtual address to form a significantly larger second virtual address, wherein portions of said second virtual address obtained from said segment registers and the page offset portion of said first virtual address comprise a virtual page address to be utilized as a search argument in a subsequent address translation procedure which procedure comprises

utilizing a subset of said virtual page address as the search argument in a set of high speed translation-look-aside buffers,

comparing a complete virtual address stored at an accessed location of said translation look-aside buffers with the complete virtual address utilized as the search argument and accessing an associated real page address in the main memory from the translation look-aside buffers if the virtual address comparison is successful,

in the event of an unsuccessful search for the virtual address in said translation look-aside buffers, continuing the search in a specified segment of storage in main memory (page frame tables) including

hashing said virtual page address,

accessing the page frame tables in main memory as a function at said hashed address, determining if the desired virtual address is at the hashed address and if not

determining if the hashed address is the initial member of a linked list of virtual addresses, all of which would produce the same hashed address,

continuing the search for the desired virtual address in said linked address list in said page frame tables until either the desired complete virtual address is found or it is determined that no such address is present,

accessing the real page address associated with said complete virtual page address, if found, in said page frame tables and utilizing said real page address as the requested real memory address.

2. An address translation method as set forth in claim 1, including

accessing additional access control bits stored in both said translation look-aside buffers and in the page frame tables associated with each translation entry for every virtual to real address translation stored therein,

accessing a plurality of lock bits stored in either said translation look-aside buffers or in the page frame tables associated with each successfully translated page, said plurality of lock bits comprising a bit for each line within an associated real page and utilizing said lock bits to control copy back and journalling operations when the current version of data stored in memory is accessed by the CPU.

3. In a data processing system, including a CPU and a large hierarchical memory a method for translating virtual memory addresses into real memory address which comprises:

the CPU generating a first virtual address comprising a segment identifier portion, a page offset portion and a byte offset portion (within the page),

using the sement identifier to access one of a plurality of segment registers pointed to by the segment identifier, each of which contains a second virtual address pointing to a large virtual block of data,

combining said second virtual address with the page offset and byte offset portions of said first virtual address to form a third virtual address wherein said third virtual address is substantially larger than said first virtual address,

utilizing said second virtual address and said page offset portion of said first virtual address as a virtual page search argument in a translation look-aside buffer (TLB) which comprises a very high speed searching mechanism for searching for a limited number of virtual addresses and for accessing real addresses stored therein which are translations of each related virtual address,

accessing said TLBs utilizing a subset of the search argument as an address,

comparing the virtual page search argument with the contents of a selected field of the accessed TLB,

upon a successful comparison, utilizing a real page address stored therein as the translation of said virtual address and,

accessing additional fields at the accessed location in said TLB for accessing and data persistence control information relevant to the data stored at the translated real page address,

and if unsuccessful initiating a search in the page frame tables in main memory,

which contain the real address corresponding to all virtual addresses utilized in the memory system at any point in time,

generating an address in the page frame tables as a function of the virtual page search argument,

accessing said page frame table at said generated address which address identifies the initial member of a linked list list of entries and comparing said virtual page search argument with a virtual page identifier stored at each entry storage location in said page frame tables until a successful comparison occurs.

4. An address translation method as set forth in claim 3 including:

retrieving the real page address, stored in and associated with a successful search, from the page frame tables together with the access and data persistence control information stored therewith and transferring said translation and control information to an appropriate storage location in the TLBs.

5. An address translation method as set forth in claim 4 wherein said step of generating an address in the page frame tables includes

generating a hash function of the virtual page search argument and

utilizing said hash function as at least a portion of the address to a particular subset of said page frame tables.

6. In a high speed electronic data processing system including a central processing unit (CPU) and a large hierarchical memory system provided with a virtual addressing space significantly larger than the actual memory, the improvement which comprises an address translation mechanism for converting virtual addresses into real memory addresses including,

means for generating a first virtual address which comprises a segment identifier field, a page offset field and a byte offset field,

a plurality of segment registers and means for loading same under program control with a second virtual address identifying a large virtual block of data,

means for accesssing one of said segments registers specified by said segment identifier field of said first virtual address,

means for concatenating the virtual address from the specified segment register with the page offset and byte offset fields of said first virtual address to form a large virtual effective address comprising an effective page address portion and a byte offset portion,

a high speed translation look-aside buffer system for storing address translation data for most recently used virtual accesses to the memory hierarchy,

means for utilizing at least a portion of said effective page address to access the translation look-aside buffer system to determine is said effective page address has been previously translated and, if so,

means for accessing the real page address from the translation look-aside buffer as the result of the translation process.

7. an address translation mechanism as set forth in claim 6 wherein said translation look-aside buffer system includes

a plurality of storage locations each of which includes means for storing;

the complete virtual page address for a particular translation, the complete real page address, and memory access and data persistence control data relevant to the particular real page of data,

means for comparing the complete effective page address which caused access of a particular storage location of the translation look-aside buffer with the virtual page address stored therein, and

in the page frame tables in main memory which contain all of the virtual to real address translations in the memory hierarchy if the search in the translation look-aside buffer system was unsuccessful.

8. An address translation mechanism as set forth in claim 7 including means for accessing the translation look-aside buffer system at an address computed from a subset of said effective page address whereby it is possible for many effective addresses to cause access of the same storage locations in said translation look-aside buffer.

9. An address translation mechanism as set forth in claim 7 wherein the means for continuing the search for a particular translation in the page frame tables includes

means for hashing the effective page address to obtain an access address into the page frame tables,

means for linking together all entries in the page frame tables which represent the virtual to real address translations of all those virtual page addresses which would hash to the same address,

means for continuing the search for a particular effective page address in the linked list until either the address is found or it is determined not to be present, and

means for transferring predetermined data relating to translation and memory control functions from the page frame tables to the appropriate location in the translation look-aside buffers concurrently with a successful translation which required using the page frame tables.

10. An address translation mechanism as set forth in claim 9 including

means in said translation look-aside buffers and the page frame tables for storing N-lock bits in each storage location wherein N is the number of lines in a page of data stored in said memory system,

means for accessing said lock bits under program control wherever an address translation operation occurs and

means for utilizing said lock bits to control copy back and journaling operations when the lock bits indicate that the particular lines(s) of data must be retained in an original form for at least a predetermined period.

11. A high speed translation look-aside buffer (TLB) mechanism for use with a virtual to real address translation system comprising

as many addressable storage locations therein as there are virtual to real address translation data entities, means in each storage location for storing;

a virtual address tag for comparison with a virtual address to be translated,

the real address in memory of the data referenced by the above virtual address, access control and identifier data relating to the data, stored at said real address in memory,

a series of "N" lock bits for use in insuring data persistence for a particular memory page wherein "N" is the number of lines in the page, p1 means for accessing said "N" lock bits stored in said translation look-aside buffers, said plurality of lock bits comprising a bit for each line within an associated real page and means for setting said lock bits to control copy back and journalling operations when the current version of data stored in memory is accessed by the CPU and

means operable under program control for accessing or altering data stored in storage location in said TLB based on a subset of the virtual address to be translated.

12. A translation look-aside buffer as set forth in claim 11 including means for processing the lock bits accompanying any real page of data which is the subject of a successful translation operation to assure that copies of lines of data in the page designated by the lock bits are retained in storage in unaltered form.