Computer aided design method and apparatus comprising means for automatically generating pin-to-pin interconnection lists between respective discrete electrical component circuits

• US 4,638,442 A
• Filed: 11/06/1984
• Issued: 01/20/1987
• Est. Priority Date: 11/09/1983
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Baker, Stephen J., Cook, Richard A., Bryant, Stewart F.
• Primary Examiner(s): Gellner, Michael L.
• Application Number:
  US06/669,207
• Time in Patent Office: 805 Days
• Field of Search: 364/488, 364/489, 364/490
• US Class Current: 716/126
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Computer aided design method and apparatus which automatically generate pin-to-pin interconnection lists between respective discrete electrical component circuits. Input devices provide for entering a list of components used, a description of those components and the circuit interconnection description. The memory store contains a library of standard component descriptions. A processing unit process the entered circuit description and selected component descriptions from storage to produce an interconnection list in the form of an individual component pin to individual component pin connection.

Claims

1. An arrangement for generating a component interconnection list for an electrical circuit, each interconnection being in the form of a link between a first individual component pin and a second individual component pin, said arrangement comprising means for entering

a component list containing any component used,

a component description of any component used inclusive of a functional pin description thereof, and

a circuit interconnection description containing elements of the form of a first array of pins of a second array of named components connected to a third array of pins of a fourth array of named components, at least one array being non-unitary,

wherein for any circuit interconnection description element in which both said first and said third arrays are non-unitary the first and third arrays have equal numbers of array elements, said arrangement furthermore containing library means for storing said component descriptions as standard component descriptions, processing means for processing, under program control, the circuit interconnection description and the list of components used while addressing said library means for accessing said component descriptions, and output means for after said processing outputting said component interconnection list.

2. An arrangement as claimed in claim 1 wherein at least one circuit interconnection description element has at least one indirect assignment (with) description block containing a Pascal language type "with" statement with respect to a fifth component array for thereto assigning a description for thereupon processing this fifth array by the processing means on the basis that any pin without an associated specified component in the circuit interconnection description is contained within said fifth array.

3. An arrangement as claimed in claim 1 or 2 wherein said circuit interconnection description further contains at least one element in the form of a sixth array of equally named pins of any component to be connected to an associated common point in the electrical circuit.

4. An arrangement as claimed in claims 1 or 2, wherein said entering comprises a declaration of all components and named signals by listing them and assigning signal names to the pins thereof prior to activating said processing means for processing the circuit description.

5. An arrangement as claimed in claims 1 or 2, in which the processing means are controlled for executing a predetermined instruction to replace a first description by a second description wherever the first description occurs.

6. An arrangement as claimed in claims 1 or 2 in which the processing means are operative for under control of a second predetermined instruction inserting the contents of a specified file at a predetermined position within the program.

7. An arrangement as claimed in claims 1 or 2, wherein said output means are visualising output means.

8. A method of generating component interconnection lists for an electrical circuit in the form of an individual component pin to individual component pin instruction comprising forming a circuit interconnection description of the form

View Dependent Claims (9)

9. A method according to claim 8, in which all components and signals are declared prior to processing the circuit description.