Secure reliable transmitting and receiving system for transfer of digital data

• US 4,638,496 A
• Filed: 04/15/1985
• Issued: 01/20/1987
• Est. Priority Date: 02/11/1982
• Status: Expired due to Term

• Current Assignee: Garold K. Jensen
• Original Assignee: Garold K. Jensen
• Inventors: Jensen, Garold K.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Glenny, Raymond C.
• Application Number:
  US06/723,316
• Time in Patent Office: 645 Days
• Field of Search: 375/51, 375/58, 375/104, 375/111, 375/113, 375/114, 375/117, 455/212, 455/222
• US Class Current: 375/351
• CPC Class Codes: G08B 19/00 Alarms responsive to two or more different undesired or abnormal conditions, e.g. burglary and fire, abnormal temperature and abnormal rate of flow
• CPC Class Codes: G08B 23/00 Alarms responsive to unspecified undesired or abnormal conditions

Abstract

A communication system for providing reliable transfer of digital data in such system as a security system between source of data 214 and user 213, and between user 213 and end use of data 215. When the false alarm rate requirement of the security system is specified in less than one in ten years, this tight requirement must also apply to the communication link even though the RF transmission path might use the very noisy 60 Hz power line. Digital data signals are transmitted only when a detection is made at source of data 214 or when user 213 outputs an action command to end of use data 215. Thus the communication system must maintain the low false alarm rate under two conditions: (1) where no data signal but noise and interference is received over long periods of time, and (2) where a data signal pulse noise is received. Receiver 212s'"'"' ability to differentiate between valid data and noise is increased by incorporating the digital data into a composite signal having a number of different signal and timing elements before it is sent. The discriminating ability of receivers 212 is further increased by including cascaded multi-stage signal processing circuits which respond to each of the elements of the composite signal but not to noise. A further barrier to false responses is provided by digital data decoders 219 which include additional signal processing circuits to recognize and accept only the valid data when it is part of a composite signal having elements of a correct count, timing and order.

Claims

1. A secure reliable transmitting and receiving system for the transfer of digital data, comprising:

means for encoding and transmitting a radio frequency carrier via a transmission medium, said transmitting means including;

(i) means for generating a radio frequency carrier;

(ii) means for frequency modulating said radio frequency carrier;

(iii) means for generating a signal having a predetermined number of clock cycles, said modulating means modulating said radio frequency carrier with said clock cycle signal such that said radio frequency carrier includes a first segment of said clock cycle signal;

(iv) means for encoding digital data having a predetermined number of bits of digital data, said modulating means modulating said radio frequency carrier with said digital data such that said radio frequency carrier includes a second segment of said digital data;

(v) means for prohibiting modulation of said radio frequency carrier by said modulating means, such that said radio frequency carrier includes a third segment having unmodulated radio frequency carrier;

(vi) means for repeated modulation of said radio frequency carrier such that said radio frequency carrier includes said first, second and third segments forming a block of information repeated a predetermined number of times, said block of information having a wave form distinct from that of unwanted noise and interference on the transmission medium;

means for receiving and demodulating said radio frequency carrier, said means including;

(i) high pass filter means for filtering out power line 60 Hz on said transmission medium;

(ii) means for amplifying and limiting a narrow band of frequencies centered on said radio frequency carrier; and

(iii) means for demodulating said radio frequency carrier to provide a demodulated signal;

circuit means associated with said receiving means for a first stage of discrimination between said block of information and noise and interference, said circuit means including;

(i) first low pass filter means for generating a signal upon receipt of said demodulated signal;

(ii) schmitt trigger circuitry for receiving said signal from said first filter means, said schmitt trigger circuitry generating an output in response to said signal from said first filter means;

(iii) flip flop circuitry for receiving said output from said schmitt trigger circuitry, said flip flop circuitry generating an first alternating output in response to said output of said schmitt trigger circuitry;

(iv) dual one shot circuitry for receiving said alternating output of said flip flop circuitry, said dual one shot circuitry generating second alternating outputs timed to coincide with the immediately following demodulated signal in response to said first alternating outputs of said flip flop circuitry;

(v) OR gate circuitry for receiving said alternating outputs of said dual one shot circuitry, said OR gate generating an output in response to said alternating outputs of said dual one shot circuitry; and

(vi) bilateral switch circuitry for receiving said outputs of said OR gate and for receiving said demodulated signal, said bilateral switch circuitry providing a demodulated signal output in response to said outputs of said OR gate circuitry;

means for a second stage of discrimination between said immediately following block of information and noise and interference including;

(i) second low pass filter means for generating a signal output upon receipt of said demodulated signal output from said bilateral switch circuitry; and

(ii) one shot circuitry for receiving said signal output from said second filter means, said one shot circuitry generating a decoder reset pulse output in response to said signal output of said second filter means;

means for a third stage of discrimination between said immediately following block of information and noise and interference including;

(i) counting means for receiving said demodulated signal output of said bilateral switch circuitry, said counting means generating a first marker pulse output at the start of said predetermined number of clock cycles, a second marker pulse output at the termination of said predetermined number of clock cycles, and a third marker pulse output at the termination of said predetermined number of digital data bits in response to said demodulated signal output from said bilateral switch circuitry; and

(ii) counting and gating means for receiving said marker pulse outputs from said counting means, said counting and gating means outputting signal clock cycles during a time interval marked by said first pulse output at the start of said predetermined number of clock cycles and said second pulse output at the termination of said predetermined number of clock cycles, said counting and gating means further outputting said digital data bits during a time interval marked by said second pulse output at the termination of said predetermined number of clock cycles and said third pulse output at the termination of the predetermined number of digital data bits, said counting and gating means further generating and outputting a shift register readout enable signal timed to immediately follow said third marker pulse in response to said third marker pulse output of said counting means, said counting and gating means further including means for receiving said decoder reset pulse output from said one shot circuitry, said counting and gating means outputting said clock cycles, said digital data bits, and said shift register readout enable signal, in response to said decoder reset pulse output of said one shot circuitry, and said counting and gating means in the absence of said decoder reset pulse output and in the absence of said clock cycles and said digital data bits blocking all output including noise and interference outputs;

receiving means for processing said gated digital data, said receiving means including;

(i) a phase locked loop frequency generator means for generating a synchronizing signal synchronous with said gated clock cycles; and

(ii) shift register means for inputting said gated digital data serially and outputting said digital data parallelly, said synchronizing signal synchronizing the inputting of said gated digital data into said shift register means; and

means for decoding said digital data, said decoding means receiving said parallel data from said shift register means.

2. A secure reliable transmitting and receiving system in accordance with claim 1, wherein said decoding means includes:

(i) bilateral switch circuitry for receiving said parallel digital data output of said shift register means and for receiving said shift register readout enable signal of said counting and gating means, said bilateral switch circuitry providing a switched parallel digital data output of short duration immediately following the time said shift register means is fully loaded with said digital data, in response to said shift register readout enable signal of said counting and gating means;

(ii) preselectable digital data decoding means for receiving said parallel digital data output of said bilateral switch circuitry, said preselectable digital decoding means providing a signal output only when said digital data matches a preselected code of said preselectable digital decoding means; and

(iii) one shot circuitry for receiving said signal output of said preselectable digital decoding means, said one shot circuitry generating the signal output in response to said signal output of said preselectable digital decoding means.

3. A secure reliable transmitting and receiving system for the transfer of digital data, comprising:

means for encoding a block of information, said block of information having a predetermined number of clock cycles, a predetermined number of bits of digital data, and a predetermined unmodulated time gap all repeated a preselected number of times, said block of information having a waveform distinct from that of noise and interference;

means for generating a radio frequency carrier;

means connected with said radio frequency carrier means for modulation of said radio frequency carrier with said block of information;

receiving means for receiving and demodulating said block of information;

circuit means associated with said receiving means for transmitting said block of information and rejecting noise and interference, said circuit means including;

(i) first low pass filter and high and low level schmitt trigger circuitry for providing a first stage of discrimination between said block of information and noise and interference in random bursts or in continuous form;

(ii) gating circuitry associated with said filter and trigger circuitry for transmitting the block of information immediately following said block of information to additional signal processing circuitry and for blocking transmission of noise and interference;

(iii) second low pass filter and one shot trigger circuitry for providing a second stage of discrimination between said immediately following block of information and noise and interference and for providing an output decoder reset pulse when the signal received by said second low pass filter and one shot trigger circuitry is said immediately following block of information and for providing no output decoder reset pulse when noise or interference is received by said filter and one-shot trigger circuitry;

(iv) divider, gating, phase locked loop clock generator, shift register and decoding circuitry for providing a third stage of discrimination between transmitted said immediately following block of information and noise and interference, said third stage of discrimination beginning only on receipt of said output decoder reset pulse signaling receipt by said second state of discrimination of said immediately following block of information rather than receipt of noise or interference, receipt of both said output decoder reset pulse and said immediately following block of information initiating count of said clock cycles and count of said digital data bits where start and termination times of said counts determine precise time periods when said clock cycles may be admitted to the phase lock loop for synchronization of said phase lock loop and the shift register and when said digital data bits may be entered into shift register, loading of said shift register terminates said counts thereby initiating off-loading of said digital data bits in said shift register in parallel to said decoding circuitry, clearing said shift register of all said digital data bits, outputting a readout enable pulse, and locking up all circuit operations of the divider, gating, phase locked loop clock generator, shift register, and decoding circuitry pending reactivation by receipt of additional said output decoder reset pulses.

4. A secure reliable transmitting and receiving system in accordance with claim 3 wherein said decoding circuitry includes:

gated receiving circuitry for receiving said parallel digital output of said shift register and for receiving said readout enable pulse, said gated receiving circuitry providing a gated parallel digital data output of short duration immediately following the time said shift register is fully loaded with said digital data in response to said readout enable pulse;

preselectable digital decoding circuitry for receiving said gated parallel digital data output of said gated receiving circuitry, said preselectable digital decoding circuitry providing a signal output only when said parallel digital data matches a preselected code of said preselectable digital decoding circuitry.