Apparatus for testing a plurality of integrated circuits in parallel

• US 4,639,664 A
• Filed: 05/31/1984
• Issued: 01/27/1987
• Est. Priority Date: 05/31/1984
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Jones, James W., San Ho, Fock, Trammell, Lyndale A., Allison, Mark D., Chiu, Anthony M.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US06/615,979
• Time in Patent Office: 971 Days
• Field of Search: 324/73 R, 324/73 AT, 324/158 F, 209/571, 209/573
• US Class Current: 324/73.1
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/31903 tester configuration

Abstract

In accordance with a broad aspect of the invention, a system is presented for parametrically and functionally testing integrated circuit devices in parallel. At least one integrated circuit device receiving channel is provided for defining a plurality of integrated circuit device test stations therealong, and means are provided for delivering parametric and functional test signals at least functionally in parallel to each of the integrated circuit device test stations. Means are provided at each test station for selectively engaging the integrated circuit devices to apply the parametric and functional test signals to the integrated circuit device at that station, and to selectively isolate the device from the test signals. Means are provided for receiving an output from each test location in response to the test signals, and means for determining from the output the parameters of each tested integrated circuit device. In accordance with the invention, means are provided for sorting the tested integrated circuit devices according to their measured or tested parameters.

Claims

1. Apparatus for parametrically and functionally testing integrated circuit devices in parallel, comprising:

at least one integrated circuit receiving channel defining a plurality of integrated circuit device test stations therealong;

load means for automatically delivering via the integrated circuit receiving channel to each of the plurality of integrated circuit device test stations a separate integrated circuit device for testing;

means for delivering parametric and functional test signals at least functionally in parallel to each of said integrated circuit device test stations;

means at each of said test stations for selectively engaging the delivered integrated circuit device to apply the parameter test signals to the integrated circuit device at said test station;

means for receiving an output from each test location in response to the test signals; and

means for determining from said output the parameters of each tested integrated circuit device.

2. The apparatus of claim 1 further comprising means for sorting said integrated circuit devices in accordance with said determined output parameters.

3. The apparatus of claim 1 wherein said at least one parallel integrated circuit device receiving channel is a plurality of parallel tracks.

4. The apparatus of claim 1 wherein said at least one parallel integrated circuit device receiving channel is two parallel tracks.

5. The apparatus of claim 4 wherein said two tracks comprise four test stations.

6. The apparatus of claim 5 wherein said four test stations are symetrically located to minimize differences in input signal paths therebetween.

7. The apparatus of claim 1 further comprising means for maintaining each of the test stations at the same temperature.

8. The apparatus of claim 7 wherein said temperature maintaining means comprises a source of air at a desired test temperature and a plenum for distributing the air at least onto the test stations.

9. The apparatus of claim 1 wherein said means at each test station for selectively engaging said integrated circuit devices comprises:

a guide bar on which are carried at least two integrated circuit devices;

a plurality of integrated circuit device contacting members;

and means for moving said device contacting members between engaging and disengaging positions of said integrated circuit devices.

10. The apparatus of claim 1 wherein the load means comprises an input shuttle to alternately load devices into the respective parallel integrated circuit receiving channels.

11. The apparatus of claim 2 wherein said means for sorting comprises:

a queue;

a shuttle to receive devices from said queue,

and a plurality of bins over which said shuttle travels to dispense said integrated circuits into selected ones of said bins according to the test measurements.

12. A method of testing integrated circuit devices, comprising:

automatically delivering to each member of a plurality of parallel connected integrated circuit test stations a separate integrated circuit device for testing;

providing parametric and functional test signals to the plurality of integrated circuit device test stations and to each delivered integrated circuit device thereby,

monitoring output signals produced from each device in response to said test signals,

selectively isolating a set of integrated circuit devices when the monitored output signals indicate a device has failed,

and repeating said test steps of providing, monitoring and isolating until the failing device is identified.