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Combined bipolar-field effect transistor resurf devices

  • US 4,639,761 A
  • Filed: 10/25/1985
  • Issued: 01/27/1987
  • Est. Priority Date: 12/16/1983
  • Status: Expired due to Term
First Claim
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1. A combined bipolar-field effect transistor RESURF device, which comprises;

  • a semiconductor substrate of a first conductivity type and having a major surface and a substrate electrode connected to the side of said substrate opposite said major surface;

    a lightly-doped epitaxial buried layer of said first conductivity type on said major surface of the substrate and having a doping level at least an order of magnitude less than that of said substrate;

    an epitaxial surface layer of a second conductivity type opposite to that of said first on said buried epitaxial layer, the doping concentration and thickness of said epitaxial surface layer being selected in accordance with the REduced SURface Field (RESURF) technique such that the product of doping concentration and epitaxial layer thickness (Nepi ×

    depi) is about 1012 atoms/cm2 ;

    a surface-adjoining base region of said first conductivity type in said epitaxial surface layer;

    a base electrode connected to said base region;

    a highly-doped buried region of said second conductivity type located beneath said base region and sandwiched between said epitaxial buried layer and said epitaxial surface layer;

    a surface-adjoining source/emitter region of said second conductivity type in said base region, the source/emitter region serving both as the source and the emitter of said combined device;

    a source/emitter electrode connected to said source/emitter region;

    a surface-adjoining drain/collector region of said second conductivity type in said epitaxial surface layer and spaced apart from said base region, the drain/collector region serving as both the drain and the collector of said combined device;

    a drain/collector electrode connected to said drain/collector region;

    a surface-adjoining channel region at least partly in a peripheral portion of said base region which is nearest said drain/collector region;

    an insulating layer on said surface layer and covering at least that part of said channel region which is in said base region; and

    a gate electrode on said insulating layer and over at least that part of said channel region which is in said base region.

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