Video display system using memory with parallel and serial access employing selectable cascaded serial shift registers

• US 4,639,890 A
• Filed: 12/30/1983
• Issued: 01/27/1987
• Est. Priority Date: 12/30/1983
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Novak, Mark F., Guttag, Karl M., Pinkham, Raymond, Redwine, Donald J., VanAken, Jerry R., Heilveil, Andrew
• Primary Examiner(s): Heckler, Thomas M.
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/567,040
• Time in Patent Office: 1,124 Days
• Field of Search: 377/76, 364/900 MS File, 364/200 MS File, 340/750, 365/189
• US Class Current: 345/559
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats

Abstract

In a computer system, an improved memory circuit is provided for accomodating video display circuits with CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accomodate any CRT screen intended to be used, and it further includes a serial shift register having a plurality of taps at locations corresponding to different preselected columns of cells in the chip. In the system, provision is included for selecting taps to unload only the portion of the shift register containing the bits of interest, whereby unused portions of the chip may be effectively excluded and the time for transferring data of interest to the CRT screen is reduced.

Claims

1. In a memory device having an array of memory cells, address terminals, a data input terminal, a data output terminal, means responsive to address signals received by said address terminals for addressing a memory cell in said array, means for writing data presented at said data input terminal to an addressed memory cell, and means for reading data contained in an addressed memory cell so that said data is presented at said data output terminal, the improvement comprising:

a register comprised of a plurality of memory cells;

means, coupled to said array and to said register, for transferring the contents of a predetermined number of memory cells in said array to memory cells in said register;

a serial output terminal;

serial output means, connected to said serial output terminal and connectable to a memory cell in said register, for communicating the contents of said selected memory cell to said serial output terminal;

means for selecting a memory cell in said register to be connected to said serial output means, responsive to an address signal received by said address terminals;

a serial clock terminal for receiving a clock signal;

shifting means, connected to said serial clock terminal, for shifting the contents of another memory cell in said register to said serial output means so that, responsive to a series of said clock signals received by said serial clock terminal, the contents of a series of memory cells in said register are presented at said serial output terminal, beginning with the contents of the memory cell in said register selected by said selecting means;

a transfer control terminal for receiving a transfer control signal; and

transfer control means, connected to said transfer control terminal and to said transferring means, for enabling and disabling said transferring means responsive to said transfer control signal, so that during such time as said transferring means is disabled, data may be written to and read from any of said memory cells in said array independently from the presentation of data at said serial output terminal.

2. The improved memory device of claim 1, wherein said serial output means comprises:

a plurality of taps, each of said taps connected to a preselected memory sell in said register; and

an output circuit connected to said serial output terminal, and selectably connectable to a tap, for presenting the contents of the preselected memory cell connected to said tap at said serial output terminal;

wherein said address terminals are adapted to receive a random address corresponding to a memory cell to be addressed in said array, and to receive a tap address, said random address and said tap address appearing at said address terminals at different points in time;

and wherein said selecting means is connected to said address terminals, and connects said output circuit to a tap selected responsive to a tap address presented at said address terminals.

3. The improved memory device of claim 2,

wherein said memory cells in said register are serially connected with respect to one another;

and wherein said shifting means is connected to said register so that, responsive to said clock signal, the contents of each memory cell in said register is shifted to the next memory cell in said register serially connected thereto.

4. The improved memory device of claim 3, further comprising:

a serial input terminal;

serial input means, connected to said serial input terminal and connected to a memory cell in said register, for writing into said memory cell connected thereto the data presented at said serial input terminal; and

means, coupled to said array and to said register, for transferring the contents of said memory cells in said register to a like number of memory cells in said array.

5. The improved memory device of claim 4, further comprising means, responsive to said address terminals, for selecting a memory cell in said register to be connected to said serial input means.

6. The improved memory device of claim 4, wherein said serial input means writes data into said memory cell connected thereto concurrently with said serial output means presenting data at said serial output terminal.

7. The improved memory device of claim 3 wherein said register comprises a first segment and a second segment, each segment having a plurality of serially connected memory cells, each segment having a tap connected to a memory cell therein, and each said segment connected to said serial clock terminal so that, responsive to a plurality of clock signals at said serial clock terminal, the contents of a plurality of said memory cells appear at said memory cells connected to said taps.

8. The improved memory device of claim 7 wherein a memory cell in said first segment is connected to a memory cell in said second segment so that the contents of said connected cell of said first segment are shifted by said shifting means into said memory cell in said second segment connected thereto.

9. A memory device comprising:

an array of memory cells, said memory cells arranged in rows and columns;

address input means, for receiving row address, column address, and serial address signals;

row address means, for selecting a row in said array responsive to said address input means receiving a row address signal;

column address means, for selecting a column in said selected row responsive to said address input means receiving a column address signal;

random input means, for writing data to said memory cell selected by said column address means;

random output means, for presenting the contents of said memory cell selected by said column address means;

a register comprises of a plurality of memory cells;

means for transferring the contents of the memory cells in said selected row of said array into the memory cells of said register;

serial output means, connected to a selected memory cell in said register, for presenting the contents of said selected memory cell in said register;

serial selecting means for selecting, responsive to said address input means receiving a serial address signal, a memory cell in said register to be connected to said serial output means;

means, responsive to a serial clock signal, for shifting to the serial output means the contents of another memory cell in said register so that, upon a series of said serial clock signals, the contents of a series of memory cells in said register will be presented by said serial output means; and

transfer control means, responsive to a transfer control signal, for selectively enabling and disabling said transferring means so that, when said transferring means is disabled, data may be written to and read from any of said memory cells in said array independently from the presentation of data by said serial output means.

10. The memory device of claim 9, further comprising:

means for sensing the contents of the memory cells in said selected row;

and wherein said transferring means, responsive to said transfer control means, transfers the sensed contents of said memory cells in said selected row to said memory cells in said register after said sensing means has sensed the contents of the memory cells in said selected row.

11. The memory device of claim 10, further comprising row address incrementing means, connected to said row address means, for incrementing the address of the selected row after a predetermined number of serial clock signals.

12. The memory device of claim 11, wherein said memory cells in said array are dynamic read/write memory cells, and wherein said sensing means, upon sensing said selected row, refreshes the contents of the memory cells in said selected row.

13. The memory device of claim 12, further comprising:

a timer;

means, responsive to said timer and connected to said row address means, for causing each of said rows in said array to be sensed after a predetermined time period, thereby periodically refreshing all of said dynamic read/write memory cells in said array.

14. The memory device of claim 9, wherein said serial selecting means comprises:

a plurality of taps, each of said taps connected to a preselected memory cell in said register;

an output circuit, connected to said serial output means; and

decode means, responsive to said address input means receiving a serial address signal, for connecting said output circuit to the tap corresponding to said serial address signal.

15. The memory device of claim 9, wherein said memory cells in said register are serially connected with respect to one another;

and wherein said register is connected to said shifting means so that, responsive to said serial clock signal, the contents of each memory cell in said register is shifted to the next memory cell in said register serially connected thereto.

16. The memory device of claim 15, further comprising:

serial input means, connected to a memory cell in said register, for writing data into said memory cell connected thereto;

and wherein said transferring means also is for transferring the contents of said memory cells in said register to a like number of memory cells in said array.

17. The memory device of claim 16, wherein said serial input means writes data into said memory cell connected thereto concurrently with the presentation of data by said serial output means.

18. The memory device of claim 16, further comprising:

means for sensing the contents of the memory cells in said selected row;

and wherein said transferring means, responsive to said transfer control means, transfers the sensed contents of said memory cells in said selected row to said memory cells in said register after said sensing means has sensed the contents of the memory cells in said selected row; and

transfer direction control means, responsive to a transfer direction signal, for controlling said transferring means so that said transferring means either transfers the contents of the memory cells in said selected row to said memory cells in said register, or transfers the contents of said memory cells in said register to said memory cells in said selected row, depending upon the transfer direction signal.

19. A data processing system comprising:

a data processing unit;

utilization means for utilizing data processed by said data processing unit; and

memory means for storing data, comprising;

an array of memory cells, said memory cells arranged in rows and columns;

address input means, for receiving row address, column address, and serial address signals;

row address means, for selecting a row in said array responsive to said address input means receiving a row address signal;

column address means, for selecting a column in said selected row responsive to said address input means receiving a column address signal;

random input means, for writing data to said memory cell selected by said column address means;

random output means, for presenting the contents of said memory cell selected by said column address means;

a register comprised of a plurality of memory cells;

means for transferring the contents of the memory cells in said selected row of said array into the memory cells of said register;

serial output means, connected to a selected memory cell in said register, for presenting the contents of said selected memory cell in said register;

serial selecting means for selecting, responsive to said address input means receiving a serial address signal, a memory cell in said register to be connected to said serial output means;

means, responsive to a serial clock signal, for shifting to the serial output means the contents of another memory cell in said register so that, upon a series of said serial clock signals, the contents of a series of memory cells in said register will be presented by said serial output means; and

transfer control means, responsive to a transfer control signal, for selectively enabling and disabling said transferring means so that, when said transferring means is disabled, data may be written to and read from any of said memory cells in said array independently from the presentation of data by said serial output means.

20. The system of claim 19, wherein said utilization means is a video display, comprising:

an input for receiving data;

output means for presenting data in a visual format; and

drive means for enabling a plurality of pixel locations in said visual format of said output means responsive to the data received by said input;

wherein said serial output means is for presenting the contents of said selected memory cell in said register to said input of said video display;

and wherein each pixel location in said visual format is associated with a memory cell in said array of said memory means.

21. The system of claim 20,

wherein a plurality of said memory means are connected in parallel to one another, each connected to said data processing unit;

and wherein said input of said video display is connected to the serial output means of said plurality of memory means.

22. The system of claim 21, further comprising:

a shift register having parallel input terminals, a serial output terminal, and a shift clock means for receiving shift clock signals, each of said parallel input terminals connected to the serial output means of one of said plurality of memory means, and said serial output of said shift register connected to said input of said video display, so that the data presented by the serial output means of said plurality of memory means is serially received by said input of said video display means, responsive to a series of shift clock signals.

23. The system of claim 20,

wherein said memory means further comprises serial input means, connected to a memory cell in said register, for writing data into said memory cell connected thereto;

wherein said transferring means also is for transferring the contents of said memory cells in said register to a like number of memory cells in said array;

and further comprising video input means, connected to said serial input means, for storing data and for presenting said stored data to said memory means.

24. The system of claim 20, wherein said data processing unit comprises:

a central processing unit; and

a graphics processing unit, connected to said central processing unit, to said address terminals of said memory means, and to said transfer control means of said memory means, for presenting said row, column and serial address signals and said transfer control signal to said memory means responsive to predetermined signals presented by said central processing unit;

wherein said random input means and said random output means of said memory means are connected to said central processing unit.

25. The system of claim 19, wherein said serial clock signal is generated by said data processing unit.

26. The system of claim 19, further comprising oscillator means, connected to said memory means, for generating said serial clock signal.