Fault determining apparatus for data transmission system

• US 4,639,917 A
• Filed: 06/22/1984
• Issued: 01/27/1987
• Est. Priority Date: 06/24/1983
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Furuta, Michihiro
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/623,705
• Time in Patent Office: 949 Days
• Field of Search: 371/15, 371/16, 371/49, 371/38, 371/10, 371/5, 371/18, 364/200, 364/900
• US Class Current: 714/45
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0778 Dumping, i.e. gathering error/state information after a fault for later diagnosis
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

A fault-determining apparatus includes parity error checking for data transferred from a main storage and an input/output unit to a CPU which has an interrupt procedure called by the detection of a parity error for recording a parity error signal in a trace recording memory along with a fault-detection signal and data transferred to a data bus from predetermined addresses of interest in the main storage and the input/output unit.

Claims

1. A fault determining apparatus for a data transmission system having a central processing unit (CPU) which transfers data to and from a main storage and an input/output unit through a data bus in accordance with information on an address command bus, said apparatus comprising:

parity generating means in each of said main storage and said input/output unit for generating and appending a parity bit to the data bus upon transfer of data bits from the respective main storage and input/output unit to the data bus,

parity checking means associated with the CPU and connected to the data bus for receiving the data bits and the parity bit and for generating a parity error signal when the parity of the received data bits does not correspond to the received parity bit,

a trace memory means connected to the data bus and the address command bus and including addressing means responsive to detection of predetermined signals on the address command bus for storing trace information of data received by said CPU from said main storage and said input/output units over a predetermined duration and for storing a transitional record of the logical state of a fault detection signal and the parity error signal from the parity checking means along with the stored data;

trace memory retrieval means for retrieving information stored in said trace memory means corresponding to stored data from a selected source address of said main storage and said input/output means along with the corresponding stored transitional record of the fault detection signal and the parity error signal; and

means for generating a record of said data transmission system based on said retrieved data and transitional record of said fault detection signal and said parity error signal retrieved by said trace memory retrieval means.

2. An apparatus according to claim 1, wherein said main storage comprises a random access memory (RAM) and a read-only memory (ROM) connected to the data bus and the address command bus along with the parity generating means for the main storage for generating and transferring the data bits and the parity bit to the data bus when the address command bus calls for transfer of data from an address in said RAM or ROM.

3. An apparatus according to claim 1, wherein said input/output unit comprises an input photocoupler, a buffer register connected to the output of the photocoupler, and a latch register connected to the buffer register and the address command bus for applied input data bits to the data bus and the parity generating means of the input/output means.

4. An apparatus according to claim 1, wherein said trace memory means comprises a trace memory connected to the data bus, an address converting circuit connected to the address command bus for detecting predetermined address signals to generate lesser significant address bits for the trace memory in correspondence to accessing by the CPU of selected addresses of interest called for at steps within a cyclic operating procedure, a counter stepped at completion of each cyclic operating procedure to generate greater significant address bits for the trace memory corresponding to successive cycles of operation.

5. An apparatus according to claim 1, wherein said memory retrieval means comprises an address setting switch, an address comparator having inputs connected to the address setting switch and the address command bus, a latch register responsive to the address comparator and connected to the data bus for receiving the retrieved data and transitional record, and a D/A converter connected to the latch output for generating an analog signal to operate the record generating means.