Line change-over circuit and semiconductor memory using the same

• US 4,641,285 A
• Filed: 08/13/1984
• Issued: 02/03/1987
• Est. Priority Date: 10/26/1983
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sasaki, Yukio, Minato, Osamu, Nishimura, Kotaro
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/640,508
• Time in Patent Office: 904 Days
• Field of Search: 365/200, 365/210, 365/174, 365/, 365/189, 365/96, 307/465, 307/468, 307/469, 371/10
• US Class Current: 365/189.02
• CPC Class Codes: G11C 29/78 using programmable devices
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

The line change-over circuit suitable for the semiconductor memory having a redundancy memory column comprises a pair of transfer gate elements provided between a first node to which a first signal to be transmitted is supplied and a pair of transmission lines, first and second switch elements. The paired transfer gate elements are controlled on a switch in complementary manner each other according to a transfer signal. The first switch element is controlled on a switch according to the transfer signal, and the second switch element is controlled on a switch according to the first signal transmitted to one of the paired transmission lines. The first switch element turns one of the transmission lines to a fixed potential like ground potential when it is kept on, and the second switch element turns the other of the transmission lines to a fixed potential when it is kept on. The line change-over circuit in the above configuration is effective to prevent a floating state of the paired transmission lines.

Claims

1. A line change-over circuit, comprising:

a first node to which a first signal to be transmitted is supplied;

a first transfer gate provided between said first node and a second node and operating as a switch according to a transfer signal;

a second transfer gate provided between said first node and a third node and operating as a switch in a complementary manner to said first transfer gate according to said transfer signal;

a first switch element coupled to said second node and turning said second node to a first fixed potential when said first transfer gate is kept off, said first switch element being operated as a switch according to said transfer signal; and

a second switch element coupled to said third node and turning said third node to a second fixed potential when said first signal is supplied to said second node.

2. A line change-over circuit as defined in claim 1, wherein said first fixed potential and second fixed potential are equal with each other.

3. A line change-over circuit as defined in claim 2, wherein said second switch element coupled to said third node operates as a switch according to said first signal.

4. A line change-over circuit as defined in claim 2, further comprising a retaining circuit coupled to said third node and giving a positive feedback signal to said third node by referring to a signal level of said third node.

5. A line change-over circuit as defined in claim 1, wherein said first transfer gate is constituted of a first channel conductive insulating gate field effect transistor, and said second transfer gate, first and second switch elements are constituted each of a channel conductive insulating gate field effect transistor contrary to said first channel conductive one.

6. A semiconductor memory, comprising;

a first node to which a selection signal formed according to address signals is supplied;

a line change-over circuit provided between said first node and second and third nodes, which comprises a first transfer gate provided between said first node and second node and operated as a switch according to a transfer signal, a second transfer gate provided between said first node and third node and operated as a a switch in a complementary manner to said first transfer gate according to said transfer signal, a first switch element coupled to said second node and turning second node to a first fixed potential when said first transfer gate is kept off, and a second switch element coupled to said third node and turning said third node to a second fixed potential when said selection signal is supplied to said second node;

a plurality of first memory cells selected according to the selection signal supplied to said second node through said line change-over circuit; and

a plurality of second memory cells selected according to the selection signal supplied to said third node through said line change-over circuit.

7. A semiconductor memory as defined in claim 6, wherein said first and second fixed potentials are kept at a level of which said first and second memory cells are not selected respectively.

8. A semiconductor memory as defined in claim 7, said line change-over circuit wherein said second switch element coupled to said third node and turning said third node to the second fixed potential operated as a switch according to said selection signal.

9. A semiconductor memory as defined in claim 7, further comprising a retaining circuit coupled to said third node and giving a positive feedback signal to said third node by referring to a signal level of said third node.

10. A semiconductor memory as defined in claim 7, each said first and second memory cells comprising a static memory cell.

11. A semiconductor memory, comprising

a plurality of first nodes, each of which is supplied with a selection signal formed according to an address signal;

a plurality of second nodes corresponding respectively to said first nodes;

a third node;

a plurality of line change-over circuits respectively provided between the first nodes and the second nodes corresponding to each other, each of which line change-over circuits comprises a first transfer gate provided between the first node corresponding thereto and the second node and operating as a switch according to a transfer signal, a second transfer gate provided between the first node corresponding thereto and said third node and operating as a switch in a complementary manner to said first transfer gate according to said transfer signal, a first switch element coupled to said first node corresponding thereto and turning said second node to a first fixed potential when said first transfer gate is kept off, and a second switch element coupled to said third node and turning said third node to a second fixed potential when a selection signal is supplied to said second node corresponding thereto;

a plurality of first memory cells selected on said selection signal supplied to the second nodes; and

a plurality of second memory cells selected on said selection signal supplied to the third node.

12. A semiconductor memory as defined in claim 11, wherein said first and second memory cells are constituted each of a memory cell capable of writing and reading data.

13. A semiconductor memory as defined in claim 12, further comprising a plurality of state setting circuits provided one-to-one to each line change-over circuit, each state setting circuit including a program element for determining a level of the transfer signal to be outputted therefrom.

14. A semiconductor memory as defined in claim 13, said program element comprising a resistance element lowered in resistance by execution of a program.

15. A semiconductor memory as defined in claim 13, said program element comprising a fuse element.

16. A semiconductor memory as defined in claim 13, further comprising:

a plurality of first data lines to which data input/output terminals of said first memory cells are coupled;

a second data line to which data input/output terminals of said second memory cells are coupled;

a common data line;

a plurality of first column switches provided between said first data lines and said common data line and operating as a switch according to a selection signal supplied to the second nodes corresponding thereto; and

a second column switch provided between said second data line and said common data line and operating as a switch according to a selection signal supplied to said third node.