High speed packet switching arrangement

• US 4,641,302 A
• Filed: 06/24/1985
• Issued: 02/03/1987
• Est. Priority Date: 06/24/1985
• Status: Expired due to Term

• Current Assignee: Racal-Datacom, Inc. (Thales SA)
• Original Assignee: Racal Data Communications Incorporated
• Inventors: Miller, William J.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Rokoff, Kenneth I.
• Application Number:
  US06/748,255
• Time in Patent Office: 589 Days
• Field of Search: 370/60, 370/94, 340/825.52
• US Class Current: 370/422
• CPC Class Codes: H04L 2012/5649 Cell delay or jitter
• CPC Class Codes: H04L 49/206 Real Time traffic
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/557 Error correction, e.g. fault recovery or fault tolerance

Abstract

A circuit arrangement is provided for switching serial data packets through a network destined for one of a plurality of possible outgoing lines. Minimal delay is achieved by shifting the data through a shift register having length equivalent to the destination address of the incoming serial data packet. The shift register addresses a memory which in turns controls a switch network so that the incoming packet is switched with minimal delay to an appropriate outbound line. By utilizing random access memory to translate from destination address to switch position, the system may be altered to correct for changes in the overall network caused by network failures or expansion network or to allow dynamic load balancing by directing data through the switch to a control computer which in turn rewrites the memory.

Claims

1. A circuit arrangement for routing incoming serial data to one of a plurality of outgoing ports, wherein said incoming serial data includes a header containing an N bit address which can be associated with one of said plurality of M outgoing ports to which said data should be routed, said circuit arrangement comprising:

a shift register having N stages and an input for receiving said serial data and an output for providing shifted data;

memory means having a parallel address word input coupled to each of said N stages to receive said N bit address and a parallel memory output;

said memory means being addressable so that when said N bit address is applied to said address word input, one of a plurality of unique output words appears at said parallel memory output, said output word being an unique identifier for one of said M outgoing ports to be selected for transmission of said shifted data; and

switching means receiving said shifted output and responsive to said parallel memory output for selecting one of said M outgoing ports for transmission of said shifted data.

2. The circuit arrangement of claim 1, further including delay means coupled between said shift register and said switching means for delaying said shifted data by a predetermined amount of time in order to synchronize receipt of said shifted data by said switching means with said selection of one of said outgoing ports.

3. The circuit arrangement of claim 1, further including decoding means for translating the output of said memory means to a one of M decoded signal.

4. The circuit arrangement of claim 1, further including latching means for latching the parallel output of said shift register when said shift register contains said destination address.

5. The circuit arrangement of claim 4, further including a computer coupled to said memory means for changing the information stored in said memory means.

6. The circuit arrangement of claim 5, wherein said switching means includes a local output coupled to said computer so that when said destination address includes a local address, said shifted data is transferred to said computer.

7. The circuit arrangement of claim 6, wherein said computer is operatively coupled to said memory means so that said computer may change the contents of said memory means responsive to said shifted data.

8. A circuit arrangement for providing rapid switching of packets to one of a plurality of output ports wherein said packets contain serial data and an N bit destination address, comprising:

an N bit shift register having a serial input for receiving said packets, a serial output and an N bit parallel output;

latching means coupled to said N bit parallel output for latching said N bit address as it passes through said shift register;

a random access memory having an N bit address coupled to said latches for addressing said memory to produce a memory output;

switching means coupled to said memory and receiving said memory output for selectively coupling one of said output ports to the serial output of said shift register;

a computer coupled to said switching means and said memory so that serial data are sent to said computer when said switching means is appropriately addressed and said memory'"'"'s contents may be altered in response to said serial data received by said computer.

9. A circuit arrangement for providing rapid switching of packets to one of a plurality of switch outputs wherein said packets contain an N bit destination address, comprising:

an N bit shift register having a serial input for receiving said packets, a serial output and an N bit parallel output;

N latches coupled to said N bit parallel output, for latching said N bit address as it passes through said shift register;

timing means, coupled to said shift register and said latches for detecting the presence of said destination address in said shift register and for directing said N latches to latch said N bit address;

a random access memory receiving said N bit address from said N latches to produce a memory output;

decoding means for decoding said memory output to produce a decoded output;

delay means coupled to said serial output and producing a delayed output therefrom;

switching means, receiving said delayed output and responsive to said decoded output, for directing said delayed output to one of a plurality of switch outputs; and

a computer coupled to said random access memory and one of said switch outputs, for altering said memory in response to packets having a predetermined destination address.