Multi-phase PSK demodulator

• US 4,641,323 A
• Filed: 02/07/1983
• Issued: 02/03/1987
• Est. Priority Date: 02/07/1983
• Status: Expired due to Fees

• Current Assignee: Chung K. Tsang
• Original Assignee: Chung K. Tsang
• Inventors: Tsang, Chung K.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/464,636
• Time in Patent Office: 1,457 Days
• Field of Search: 375/80, 375/81, 375/83, 375/84, 375/85, 375/86, 375/111, 375/113, 375/114, 375/118, 375/119, 329/110, 329/112, 455/205, 455/207
• US Class Current: 375/324
• CPC Class Codes: H04L 27/2276 using frequency multiplication or harmonic tracking
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A multi-phase PSK (phase shift key) demodulator is applied to recover a binary encoded serial data from a continuous multi-phase modulated signal source. This demodulator mainly comprises a carrier detect, a hard limiter, a harmonic phase-locked clock regenerator, a digital multi-phase demodulator, a data clock divider and a reference phase synchronizer. The digital multi-phase demodulator applies the output of the harmonic phase-locked clock regenerator and N-th phase rectangular wave PSK signal to produce a demodulated binary encoded parallel data. Then the demodulated parallel data is converted into a serial data via a parallel to serial converter. The reference phase synchronizer can obtain a reference signal through the information of the leader preamble or continuous distributed sync words. Thus a retransmission is not required for phase resynchronization. The regeneration of carrier related clock signal and data demodulation are independent of data pattern if the input signal is preemphasized or conditioned.

Claims

1. A multi-phase PSK (phase shift key) demodulator for operating upon an input signal representing a continuous N-th phase (N=2ⁿ, n being a natural number) PSK modulated source with a predetermined sync preamble and outputting a binary encoded serial data independent of data pattern when said input signal being preemphasized or conditioned, said demodulator comprising:

(a) a full wave rectifier means slicing the input signal into an uni-polar signal,

(b) a first hard limiter means converting the uni-polar signal into a rectangular clock tracking signal source,

(c) a harmonic clock regenerator means receiving said rectangular clock tracking signal source for reproducing a N-th time harmonic frequency source of the carrier independent of signal'"'"'s data pattern and feeding said harmonic frequency source to a multi-phase translator and reference phase synchronizer,

(d) a second hard limiter means converting the input signal into a N-th phase rectangular wave PSK signal,

(e) said digital multi-phase translator means responding to clock output of the harmonic clock regenerator and rectangular PSK signal output of second hard limiter for producing a binary parallel data,

(f) a frequency divider means dividing said N-th time harmonic frequency source into a serial data clock,

(g) a parallel to serial converter means converting said parallel data into a serial one with the application of data clock,

(h) a carrier detect means generating a one-shot signal during the preamble period to control the frequency divider and enable a reference phase synchronizer, and,

(i) said reference phase synchronizer means extracting the reference phase signal from the preamble sync pattern to synchronize said digital multi-phase translator and frequency divider.

2. A multi-phase PSK demodulator of claim 1 wherein:

(a) said harmonic clock regenerator means comprises a non-linear phase locked loop comparing phases only during one directional edges of said clock tracking source applied to its input,

(b) said frequency divider means comprises either (i) a digital counter for most divisible ratios or (ii) a phase locked loop dividing circuit for all general cases,

(c) said digital multi-phase translator means comprises a decoding circuit converting the N-th rectangular PSK signal into a parallel binary data, a counter generating a carry signal indicating decoded data ready and an error signal output indicating any illegal N-th rectangular PSK sequence or a validation of phase slip, and,

(d) said reference phase synchronizer means comprises of a shift register and leader pattern correlator to sort the sync pattern during preamble period and to generate a chain of sync pulses synchronizing said digital multi-phase translator means and frequency divider.

3. A multi-phase PSK demodulator of claim 2 wherein said non-linear phase locked loop means further comprises:

(a) a delay device means delaying the input signal'"'"'s edge of half phase segment (i.e. 1/2 Nf second, f is the modulation rate),

(b) a synchronous latch means storing the input signal'"'"'s one-direction edge and being reset by a pulse generated from a sampling latch,

(c) said sampling latch means accepting a clock signal feedback from the following stated voltage controlled oscillator output to generate a pulse at its output after an one directional edge latched by said synchronous latch,

(d) a sequential phase/frequency detector means comparing edges'"'"' phases from said delay device output and sampling latch,

(e) a low pass filter means filtering said sequential phase/frequency detector'"'"'s output into a direct current signal, and,

(f) a voltage controlled oscillator means accepting said low pass filter'"'"'s output to generate a frequency source of N·

f Hz at its output and requiring the frequency maximum limited to less than 2 Nf Hz and minimum limited to more than 0.5 Nf Hz.

4. A multi-phase PSK demodulator of claim 1 or 2 wherein said frequency divider means for general cases comprising:

(a) a dividing by N counter means dividing said N-th time harmonic frequency by N to have a carry signal output and accepting synchronous reset from a said reference phase signal,

(b) a dividing by n counter means dividing a voltage controlled oscillator output by n and having a carry signal output,

(c) a dividing by M counter means dividing said carry output of said `dividing by n counter` by M (where M is a number of modulated symbols of a sync word) and having a carry signal output,

(d) a first selector means accepting the carry signal from said `dividing by N counter` as input during data field period and said reference phase signal as input during preamble period,

(e) a second selector means accepting the carry signal from said `dividing by n counter` as input during data field period and from said `dividing by M counter` as input during preamble period,

(f) a phase detector means comparing phases from both said selectors'"'"' outputs with a locking frequency of f Hz during data field period and f/M Hz during preamble period,

(g) a low pass filter means accepting said phase detector'"'"'s output into a direct current signal, and,

(h) said voltage controlled oscillator means receiving said low pass filter'"'"'s output to generate a n·

f Hz signal output.

10. A multi-phase PSK demodulator of claim 1 or 5 wherein said frequency divider, translator, parallel to serial converter, and reference phase synchronizer means is substituted by a processor type element which itself is a logic means.

5. A multi-phase PSK (phase shift key) demodulator with a distributed reference phase synchronizer for operating upon an input signal representing a continuous N-th phase (N=2², n being a natural number) PSK modulated source with a predetermined sync preamble and distributed sync words in data field structure and outputting a phase self-synchronized binary enboded serial data independent of data pattern when said input signal being preemphasized or conditioned, said demodulator comprising:

(a) a full wave rectifier means slicing the input signal into an uni-polar signal,

(b) a first hard limiter means converting the uni-polar signal into a rectangular clock tracking signal source,

(c) a harmonic clock regenerator means receiving said rectangular clock tracking signal source for reproducing a N-th time harmonic frequency of the carrier independent of signal'"'"'s data pattern and feeding said harmonic frequency to a multi-phase translator and reference phase synchronizer,

(d) a second hard limiter means converting the input signal into a N-th phase rectangular wave PSK signal,

(e) said digital multi-phase translator means responding to clock output of the harmonic clock regenerator and rectangular PSK signal output of second hard limiter for producing a binary parallel data,

(f) a frequency divider means dividing said N-th time harmonic frequency source into a serial data clock,

(g) a parallel to serial converter means converting said parallel data into a serial one with the application of data clock,

(h) a carrier detect means generating a one-shot signal during the preamble period to control the frequency divider and enable a reference phase synchronization, and,

(i) said reference phase synchronizer means extracting the reference phase signal from the preamble sync pattern and the distributed sync word in data field to synchronize said digital multi-phase translator and frequency divider.

6. A multi-phase PSK demodulator of claim 5 wherein:

(a) said distributed sync word in a data field structure comprises many sync symbols and an asymmetric data pattern, and,

(b) said data field structure comprises a frame structure which has X sub-frames and each sub-frame has Y modulated symbols wide with a sync symbol at the end.

7. A multi-phase PSK demodulator of claim 5 wherein:

(a) said reference phase synchronizer means comprises of a shift register and leader pattern correlator to sort the sync pattern during preamble period and comprises a distributed sync word correlator and reframing circuit to sort said distributed sync word during data field, and,

(b) said reference phase signal means comprises of the output of leader pattern correlator during preamble period and distributed sync word correlator output during data field to synchronize said multi-phase translator and frequency divider.

8. A multi-phase PSK demodulator of claim 5, or 7 wherein said reference phase synchronizer comprises:

(a) said distributed sync word correlator checking said sync word at the end of a frame data,

(b) a reframe request signal line carrying a signal generated from said distributed sync word correlator requesting a reframe action at the reframe circuit for any detected sync word error (phase slip or misalignment),

(c) said reframe circuit responding to said reframe request signal from said distributed sync word correlator for searching a correct time slot of the distributed sync word,

(d) a reframe signal line carrying a signal generated at said correct time slot by the reframe circuit to reset the distributed sync word correlator and indirectly to synchronize the digital multi-phase translator and frequency divider, and,

(e) said distributed sync word correlator also being reset by the output of leader pattern correlator during preamble period.

9. A multi-phase PSK demodulator of claim 5, wherein said parallel to serial converter responding to a time multiplexing frame structure data input and a distributed sync reference phase signal for producing a time demultiplexed multi-channel serial data.

11. A multi-phase PSK demodulator of claim 5 wherein said harmonic clock regenerator means comprises a non-linear phase locked loop comprising phases only during positive edges of said clock tracking source applied to its input further including:

(a) a delay means delaying the input signal'"'"'s edge of half phase segment (i.e. 1/2 Nf second, f is the modulation rate),

(b) a synchronous latch means storing the input signal'"'"'s positive edge and being reset by a pulse generated from a sampling latch,

(c) a sampling latch means accepting a clock signal feedback from a voltage controlled oscillator output to generate a pulse at its output after a positive edge latched by said synchronous latch,

(d) a sequential phase/frequency detector means comparing positive edges'"'"' phases from said delay device output and sampling latch,

(e) a low pass filter means filtering said sequential phase/frequency detector output into a direct current signal, and,

(f) said voltage controlled oscillator means accepting said low pass filter output to generate a frequency source of N·

f Hz at its output and requiring the frequency source of maximum limited to less than 2 Nf Hz and minimum limited to more than 0.5 Nf Hz.

12. A method of achieving reference phase synchronization without retransmission after a phase slip or misalignment at a multi-phase PSK demodulator, comprising inputting a multi-phase PSK modulated signal source containing distributed sync words, correlating and verifying the distributed sync word for a proper reference phase position by a distributed sync word correlator, responding to a request of reframing due to a phase slip or misalignment indicated by the distributed sync word correlator as to resort a correct time slot of the distributed sync word by a reframe circuit, and reseting the sync word word correlator and synchronizing internal operations of said multi-phase PSK demodulator at said correct time slot provided by the reframe circuit to complete the reference phase synchronization.