Multi-phase PSK demodulator
First Claim
1. A multi-phase PSK (phase shift key) demodulator for operating upon an input signal representing a continuous N-th phase (N=2n, n being a natural number) PSK modulated source with a predetermined sync preamble and outputting a binary encoded serial data independent of data pattern when said input signal being preemphasized or conditioned, said demodulator comprising:
- (a) a full wave rectifier means slicing the input signal into an uni-polar signal,(b) a first hard limiter means converting the uni-polar signal into a rectangular clock tracking signal source,(c) a harmonic clock regenerator means receiving said rectangular clock tracking signal source for reproducing a N-th time harmonic frequency source of the carrier independent of signal'"'"'s data pattern and feeding said harmonic frequency source to a multi-phase translator and reference phase synchronizer,(d) a second hard limiter means converting the input signal into a N-th phase rectangular wave PSK signal,(e) said digital multi-phase translator means responding to clock output of the harmonic clock regenerator and rectangular PSK signal output of second hard limiter for producing a binary parallel data,(f) a frequency divider means dividing said N-th time harmonic frequency source into a serial data clock,(g) a parallel to serial converter means converting said parallel data into a serial one with the application of data clock,(h) a carrier detect means generating a one-shot signal during the preamble period to control the frequency divider and enable a reference phase synchronizer, and,(i) said reference phase synchronizer means extracting the reference phase signal from the preamble sync pattern to synchronize said digital multi-phase translator and frequency divider.
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Abstract
A multi-phase PSK (phase shift key) demodulator is applied to recover a binary encoded serial data from a continuous multi-phase modulated signal source. This demodulator mainly comprises a carrier detect, a hard limiter, a harmonic phase-locked clock regenerator, a digital multi-phase demodulator, a data clock divider and a reference phase synchronizer. The digital multi-phase demodulator applies the output of the harmonic phase-locked clock regenerator and N-th phase rectangular wave PSK signal to produce a demodulated binary encoded parallel data. Then the demodulated parallel data is converted into a serial data via a parallel to serial converter. The reference phase synchronizer can obtain a reference signal through the information of the leader preamble or continuous distributed sync words. Thus a retransmission is not required for phase resynchronization. The regeneration of carrier related clock signal and data demodulation are independent of data pattern if the input signal is preemphasized or conditioned.
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Citations
12 Claims
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1. A multi-phase PSK (phase shift key) demodulator for operating upon an input signal representing a continuous N-th phase (N=2n, n being a natural number) PSK modulated source with a predetermined sync preamble and outputting a binary encoded serial data independent of data pattern when said input signal being preemphasized or conditioned, said demodulator comprising:
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(a) a full wave rectifier means slicing the input signal into an uni-polar signal, (b) a first hard limiter means converting the uni-polar signal into a rectangular clock tracking signal source, (c) a harmonic clock regenerator means receiving said rectangular clock tracking signal source for reproducing a N-th time harmonic frequency source of the carrier independent of signal'"'"'s data pattern and feeding said harmonic frequency source to a multi-phase translator and reference phase synchronizer, (d) a second hard limiter means converting the input signal into a N-th phase rectangular wave PSK signal, (e) said digital multi-phase translator means responding to clock output of the harmonic clock regenerator and rectangular PSK signal output of second hard limiter for producing a binary parallel data, (f) a frequency divider means dividing said N-th time harmonic frequency source into a serial data clock, (g) a parallel to serial converter means converting said parallel data into a serial one with the application of data clock, (h) a carrier detect means generating a one-shot signal during the preamble period to control the frequency divider and enable a reference phase synchronizer, and, (i) said reference phase synchronizer means extracting the reference phase signal from the preamble sync pattern to synchronize said digital multi-phase translator and frequency divider. - View Dependent Claims (2, 3, 4, 10)
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5. A multi-phase PSK (phase shift key) demodulator with a distributed reference phase synchronizer for operating upon an input signal representing a continuous N-th phase (N=22, n being a natural number) PSK modulated source with a predetermined sync preamble and distributed sync words in data field structure and outputting a phase self-synchronized binary enboded serial data independent of data pattern when said input signal being preemphasized or conditioned, said demodulator comprising:
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(a) a full wave rectifier means slicing the input signal into an uni-polar signal, (b) a first hard limiter means converting the uni-polar signal into a rectangular clock tracking signal source, (c) a harmonic clock regenerator means receiving said rectangular clock tracking signal source for reproducing a N-th time harmonic frequency of the carrier independent of signal'"'"'s data pattern and feeding said harmonic frequency to a multi-phase translator and reference phase synchronizer, (d) a second hard limiter means converting the input signal into a N-th phase rectangular wave PSK signal, (e) said digital multi-phase translator means responding to clock output of the harmonic clock regenerator and rectangular PSK signal output of second hard limiter for producing a binary parallel data, (f) a frequency divider means dividing said N-th time harmonic frequency source into a serial data clock, (g) a parallel to serial converter means converting said parallel data into a serial one with the application of data clock, (h) a carrier detect means generating a one-shot signal during the preamble period to control the frequency divider and enable a reference phase synchronization, and, (i) said reference phase synchronizer means extracting the reference phase signal from the preamble sync pattern and the distributed sync word in data field to synchronize said digital multi-phase translator and frequency divider. - View Dependent Claims (6, 7, 8, 9, 11)
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12. A method of achieving reference phase synchronization without retransmission after a phase slip or misalignment at a multi-phase PSK demodulator, comprising inputting a multi-phase PSK modulated signal source containing distributed sync words, correlating and verifying the distributed sync word for a proper reference phase position by a distributed sync word correlator, responding to a request of reframing due to a phase slip or misalignment indicated by the distributed sync word correlator as to resort a correct time slot of the distributed sync word by a reframe circuit, and reseting the sync word word correlator and synchronizing internal operations of said multi-phase PSK demodulator at said correct time slot provided by the reframe circuit to complete the reference phase synchronization.
Specification