Multilayer circuit board manufacturing

• US 4,642,160 A
• Filed: 08/12/1985
• Issued: 02/10/1987
• Est. Priority Date: 08/12/1985
• Status: Expired due to Term

• Current Assignee: Laservia Corporation
• Original Assignee: Interconnect Technology, Inc.
• Inventors: Burgess, Larry W.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US06/764,497
• Time in Patent Office: 547 Days
• Field of Search: 29/852, 29/855, 29/874, 29/883-885, 156/630, 156/633, 156/634, 156/644, 156/652, 156/655, 156/656, 156/659.1, 156/668, 156/901, 156/902, 174/68.5, 427/96-98, 430/313-316, 430/318
• US Class Current: 216/18
• CPC Class Codes: H05K 1/0269 for visual or optical inspection
• CPC Class Codes: H05K 2201/0355 Metal foils
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09781 Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 2201/09918 Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
• CPC Class Codes: H05K 2203/0554 Metal used as mask for etching vias, e.g. by laser ablation
• CPC Class Codes: H05K 3/0035 of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/0052 Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/025 by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
• CPC Class Codes: H05K 3/427 initial plating of through-holes in metal-clad substrates
• CPC Class Codes: H05K 3/4652 Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4679 Aligning added circuit layers or via connections relative to previous circuit layers
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A circuit board is manufactured from a core layer having a conductor run layer overlying the core layer on one side thereof, and a continuous layer of dielectric material overlying the conductor run layer, by forming a continuous outer layer of conductive material over the layer of dielectric material. Material of the continuous outer layer is removed at a predetermined location, and the dielectric material that is thus exposed is also removed so as to form an opening through which the conductor run layer is exposed. Conductive material is deposited into the opening to at least the level of the outer conductor layer, whereby the conductor run layer is connected to the outer layer of conductive material.

Claims

1. A method of manufacturing a circuit board, comprising forming a conductor run layer on one face of a core layer, depositing a layer of dielectric material over the conductor run layer, depositing an outer layer of conductive material over the layer of dielectric material, locally removing material of the outer layer so as to expose the dielectric material, removing the exposed dielectric material so as to form an opening through which the conductor run layer is exposed, and depositing conductive material into said opening so as to establish electrical connection between the conductor run layer and the outer layer of conductive material.

2. A method according to claim 1, wherein the conductor run layer is formed by laminating a foil of conductive material to the core layer and selectively etching the foil of conductive material to define the conductor runs of the conductor run layer.

3. A method according to claim 1, wherein the layer of dielectric material is deposited as a unitary sheet over the conductor run layer and the outer layer of conductive material is deposited as a unitary sheet of conductive material over the unitary sheet of dielectric material, and the unitary sheets of dielectric material and conductive material are laminated to the core under heat and pressure.

4. A method according to claim 1, wherein the conductive material is deposited into said opening by electroless deposition of a layer of conductive material over the entire surface of the outer layer of conductive material, and the method further comprises selectively etching the electrolessly deposited material and the outer layer of conductive material to define an outer conductor run layer.