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Source-side self-aligned gate process

  • US 4,642,259 A
  • Filed: 04/26/1985
  • Issued: 02/10/1987
  • Est. Priority Date: 04/26/1985
  • Status: Expired due to Fees
First Claim
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1. A source side self-aligned gate process for fabricating an integrated circuit device comprising:

  • providing a substrate having a reference surface and an active device region in the material of the substrate;

    masking the substrate surface over the active device region with an ion-opaque, removable first mask layer;

    forming a pair of spaced-apart openings in the mask within the active device region;

    implanting ions through the pair of openings into the active device region to form a pair of self-aligned implant regions spaced apart from a gap having a first length defined by the spacing of the openings;

    depositing a first dielectric layer through the mask openings onto the substrate surface so as to cover the self-aligned implant regions;

    removing the first mask layer and any of the first dielectric layer deposited thereon while leaving first and second spaced-apart dielectric patches covering the self-aligned implant regions and aligned therewith;

    masking the substrate surface and the first and second dielectric patches with a second mask layer;

    forming a single opening in the second mask layer in the active device region in a location and of a length encompassing a portion of said gap and an overlappingly intersecting an adjoining portion of the first patch;

    depositing a second dielectric layer through said single mask opening onto the substrate;

    removing the second mask layer and any of the second dielectric layer deposited thereon while leaving a third dielectric patch covering said portions of the gap and the first patch and spaced from the second patch to define a reduced gap therebetween;

    depositing a gate conductor material in the gap to form a gate having a gate contact in contact with the substrate material in the reduced gap, the gate contact having a length defined by the spacing across the reduced gap between the second and third patches of dielectric material.

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