Source-side self-aligned gate process

• US 4,642,259 A
• Filed: 04/26/1985
• Issued: 02/10/1987
• Est. Priority Date: 04/26/1985
• Status: Expired due to Fees

• Current Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Gleason, Kimberly R., Vetanen, William A., Beers, Irene G.
• Primary Examiner(s): Kittle, John E.
• Assistant Examiner(s): RYAN, PATRICK J
• Application Number:
  US06/727,485
• Time in Patent Office: 655 Days
• Field of Search: 430/312, 430/313, 430/314, 430/316, 430/317, 430/319, 430/323, 430/324, 430/329, 29/576 B, 29/576 C, 29/578, 148/1.5, 148/187, 428/137, 428/901
• US Class Current: 257/284
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/0891 of field-effect transistors with Schottky gate
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/66871 Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
• CPC Class Codes: H01L 29/8128 with recessed gate
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 428/24322 Composite web or sheet

Abstract

A self-aligned gate GaAsFET fabrication process and structure are disclosed in which the gate metallization is offset to one side of the channel aligned with the source-side implant. The arrangement is advantageously provided by a photolithographic fabrication process in which a pair of self-aligned implants are made, before gate metallization. As an intermediate step, a first etch-resistant ZrO patch is deposited over at least one of the self-aligned implants aligned therewith. Then, a second such patch is deposited which overlaps the other self-aligned implant and extend a distance over the channel between the two implants. The first and second patches are thereby spaced closer together (e.g., 0.5 μm) than the implants (e.g., 1.0 μm). The patches fix the gate length at less than implant spacing and offset the gate metallization along the source-side self-aligned implant, away from the drain implant. The gate is preferably recessed. This arrangement effectively provides asymmetrical doping concentrations on opposite sides of the gate conductor, which enables improvement in both gate-drain capacitance C_gd and source-gate resistance R_s.

Claims

1. A source side self-aligned gate process for fabricating an integrated circuit device comprising:

providing a substrate having a reference surface and an active device region in the material of the substrate;

masking the substrate surface over the active device region with an ion-opaque, removable first mask layer;

forming a pair of spaced-apart openings in the mask within the active device region;

implanting ions through the pair of openings into the active device region to form a pair of self-aligned implant regions spaced apart from a gap having a first length defined by the spacing of the openings;

depositing a first dielectric layer through the mask openings onto the substrate surface so as to cover the self-aligned implant regions;

removing the first mask layer and any of the first dielectric layer deposited thereon while leaving first and second spaced-apart dielectric patches covering the self-aligned implant regions and aligned therewith;

masking the substrate surface and the first and second dielectric patches with a second mask layer;

forming a single opening in the second mask layer in the active device region in a location and of a length encompassing a portion of said gap and an overlappingly intersecting an adjoining portion of the first patch;

depositing a second dielectric layer through said single mask opening onto the substrate;

removing the second mask layer and any of the second dielectric layer deposited thereon while leaving a third dielectric patch covering said portions of the gap and the first patch and spaced from the second patch to define a reduced gap therebetween;

depositing a gate conductor material in the gap to form a gate having a gate contact in contact with the substrate material in the reduced gap, the gate contact having a length defined by the spacing across the reduced gap between the second and third patches of dielectric material.

2. A gate process according to claim 1 including:

masking the reference surface and the patches of dielectric material with a third mask layer;

forming a single opening in the third mask layer in a location and of a length encompassing said reduced gap and adjoining portions of the second and third dielectric patches; and

depositing said gate conductor material through the opening in the second mask.

3. A gate process according to claim 2, including:

composing the substrate of an etchable material;

composing the dielectric layer of a non-etchable material; and

prior to the gate conductor deposition step, etching the substrate material through the opening in the third mask to form a recess in the substrate to predetermined depth in said active region and having at said reference surface a maximum length defined by the gap between the two patches of dielectric material.

4. A gate process according to claim 3 including:

selecting for said substrate material a crystalline material having a crystallographic structure which etches anisotropically;

selecting as said reference surface a face of the material such that the material etches at a non-normal inclination to the reference surface; and

orienting the gate so that the recess is formed with sides inclined inward proceeding depthwise into the substrate so as to space the gate conductor material away from the gate implant regions at said predetermined depth.

5. A gate process according to claim 1, including:

composing said dielectric layer of a non-etchable material; and

depositing a preliminary dielectric layer of etchable material on the substrate surface prior to the first masking step; and

prior to the gate conductor deposition step, etching the preliminary dielectric layer through the opening in the second mask to expose the substrate material.

6. A gate process according to claim 1 including:

composing the substrate of a first material etchable by a first etchant;

depositing a preliminary dielectric layer, composed of a second material etchable by a second etchant, on the reference surface of the substrate prior to the first masking step;

selecting for the deposition of the dielectric layer defining said patches, a third material which is resistant to the first and second etchants; and

etching the preliminary dielectric layer and the substrate with the first and second etchants, respectively, to form a recess in the reduced gap having a length defined by the spacing of the second and third patches.

7. A gate process according to claim 6 in which the first material is GaAs;

the second material includes Si₃ N₄ ; and

the third material is ZrO.

8. A gate process according to claim 1 including annealing the substrate prior to the step of depositing gate material.

9. A gate process according to claim 1 including selecting for said dielectric layer and for said substrate, materials having approximately equal coefficients of thermal expansion.

10. A gate process according to claim 9 in which the substrate material is GaAs and the dielectric material is ZrO.

11. A gate process according to claim 1 including sizing the opening in the second mask layer so that the second length is greater than the first length.

12. A source-side self-aligned gate process for making submicron gates in integrated circuits, comprising:

providing a semi-insulating substrate having a reference surface;

depositing a first dielectric layer over said surface;

doping a first defined area of the substrate to a first dopant concentration and a first depth;

doping a pair of second defined areas of the substrate, overlapping the first defined area and spaced apart therein at a first spacing, to a second concentration and a second depth that are greater than the concentration and depth of doping in the first area;

doping a pair of third defined areas of the substrate, to a third dopant concentration less than the second concentration and a depth greater than the first depth, the third areas overlapping the second areas within the first area and spaced apart therein to define inward dopant boundaries between the first and third concentrations at a second spacing less than the first spacing;

depositing a second dielectric layer atop the first dielectric layer, over one of the third areas so as to define a first dielectric patch having a first edge which is aligned with one of said inward dopant boundaries;

depositing a third dielectric layer over the other third area and a limited adjoining portion of the first area to define a second dielectric patch having an edge in the first area spaced apart from the edge of the first dielectric patch to form a gap having a length less than said second spacing; and

depositing a conductive gate material in the gap to form a gate contact with the first area which is aligned with the inward boundary of said one third area and spaced inwardly from the inward boundary of the other of the third areas.

13. A process according to claim 12, including selectively removing the first dielectric layer in the gap, leaving the second and third dielectric patches substantially intact, prior to deposition of the conductive material.

14. A process according to claim 12, including selectively etching the first dielectric layer and the substrate material within the gap, the second and third dielectric layers being etch-resistant, to form a recess in the substrate prior to deposition of the conductive material.

15. A process according to claim 12 including:

depositing a fourth dielectric layer over said surface including over said first, second and third areas, the first and fourth dielectric layers each being formed of a dielectric material removable by a predetermined etchant and the second and third dielectric layers being formed of a different dielectric material resistant to said etchant;

masking the fourth dielectric layer with a mask layer and forming an opening in the mask layer approximately aligned with said first area;

the mask layer being formed of a mask material resistant to said etchant and otherwise removable;

etching through the opening with said predetermined etchant to remove portions of the first and fourth dielectric layers exposed within the gap and thereby expose a portion of the reference surface of the substrate;

etching the exposed portion of the substrate surface so as to form, within the gap, a recess in the substrate having a predetermined depth from the reference surface;

depositing said conductive gate material through the opening into the gap and the recess; and

removing the mask material.

16. A source side self-aligned gate for making submicron gates in integrated circuits, comprising:

providing a semi-insulating substrate having a reference surface;

depositing a first dielectric layer over said surface;

applying a first layer of photoresist over the first dielectric layer and forming a pair of closely spaced apart openings extending through the photoresist to expose a surface portion of the first dielectric layer through said openings;

doping a pair of areas of the substrate to define two implanted regions having implant boundaries substantially aligned with said openings and spaced apart to define a first gap between the regions;

depositing a second dielectric layer on the photoresist and within the openings atop the surface portion of the first dielectric layer exposed therein;

removing the first layer of photoresist, thereby removing any of the second dielectric layers deposited thereon and leaving a pair of areas of the second dielectric layer atop the first dielectric layer extending over the pair of implanted regions and having dielectric boundaries spaced closely apart in accordance with the spacing of the openings;

applying a second layer of photoresist over the first and second dielectric layers;

positioning and forming a first single opening extending through the second photoresist layer so as to expose a portion of only one of the pair of areas of the second dielectric layer and an adjoining surface portion of the first dielectric layer spaced apart within the first gap from the other of the pair of areas of the second dielectric layer;

depositing a third dielectric layer on the photoresist and the surface portions of the first and second dielectric layers exposed within the first single opening;

removing the second layer of photoresist, thereby removing the third dielectric layer deposited thereon and leaving an area of the third dielectric layer atop said exposed portions of the first and second dielectric layers, the second and third dielectric layers together extending over the pair of implanted regions and having dielectric boundaries spaced closely apart to define a second gap of reduced length in accordance with the spacing of the openings;

masking the surface with a mask layer and forming a second, single opening therethrough approximately in alignment with a portion of gap between the implanted regions to expose a surface of the first dielectric layer between said dielectric boundaries;

selecting for the first and third dielectric layers a material which is removable by a predetermined etchant and selecting for the mask layer and second dielectric layer materials which are resistant to said etchant;

etching through the second opening with the predetermined etchant selectively to remove the first dielectric layer and thereby expose a portion of the substrate bounded by the boundaries of said second dielectric layer;

etching the exposed portion of the substrate surface so as to form a recess, the substrate in the gap having a predetermined depth from the reference surface;

removing the mask material;

depositing a conductive gate material within at least the second gap and the recess.

17. A gallium arsenide integrated circuit gate structure, comprising:

a GaAs substrate having a reference surface;

a first region within the substrate doped to a first dopant concentration;

a pair of second regions spaced apart about and adjoining opposite sides of the first region within the substrate, each second region being doped to a second dopant concentration greater than the first concentration and defining first and second dopant gradient boundaries on opposite sides of the first region extending depthwise into the substrate from the reference surface;

a dielectric layer covering a portion of the substrate surface including each of the second doped regions and a portion of the first doped region, the dielectric layer having a gap in the first region defined by spaced apart first and second edges; and

conductive gate material defining a gate in contact with the substrate in the gap between the first and second edges of the dielectric layer;

the first edge being aligned with the first dopant gradient boundary and the second edge being spaced between the dopant gradient boundaries so as to define a gate length less than the spacing between the two second doped regions and to space the conductive gate material away from the second gradient boundary.

18. A GaAs gate structure according to claim 17 including means defining a channel recessed depthwise into the substrate in the first doped region between said two edges of the dielectric layer, the conductive gate material filling the channel.

19. A GaAs gate structure according to claim 18 in which the channel has a sidewall adjoining the first edge of the dielectric layer at the reference surface and being inclined inwardly of the channel proceeding downward so as to space the conductive gate material away from the first gradient boundary.

20. A GaAsFET according to claim 17 in which the second regions define a source region and a drain region, the gate being offset in the first region so as to be aligned with the gradient boundary of the source region and spaced from the drain region.