Intruder detection and deterrent system

• US 4,642,612 A
• Filed: 06/18/1984
• Issued: 02/10/1987
• Est. Priority Date: 06/18/1984
• Status: Expired due to Fees

• Current Assignee: Herschel W. Crump
• Original Assignee: Herschel W. Crump
• Inventors: Crump, Herschel W.
• Primary Examiner(s): Rowland, James L.
• Assistant Examiner(s): TUMM, BRIAN
• Application Number:
  US06/621,704
• Time in Patent Office: 967 Days
• Field of Search: 340/506, 340/507, 340/508, 340/523, 340/511, 340/521, 340/526, 340/541
• US Class Current: 340/541
• CPC Class Codes: G08B 13/00 Burglar, theft or intruder alarms

Abstract

The present invention discloses a staged system for both detecting and deterring intruders into a closed space such as a home or business. The staged system provides varying responses according to the degree of penetration of the intruder into the protected area.

Claims

1. An intruder deterrence system for protecting enclosed premises, said system comprising:

at least three sensors arranged to be placed incrementally along a path of probable ingress of a potential intruder into the protected premises;

said sensors adapted to emit an electrical signal upon passage thereby by any person;

latching means connected to the signal output of each said sensor and arranged to generate a signal and then latch-over upon receiving the first signal generated by said sensor, and further adapted to thereafter prevent additional signals from said sensor being passed through said latching means until said latching means is reset;

an OR gate means having inputs operably connected to the signal outputs of all of said latching means, and a signal output;

a first staged response circuit connected operably to the output of said OR gate means and having timing means therein including an adjustable timer with a signal input and a signal output, for generating after a predetermined period a first staged response signal in response to a signal received from said OR gate means;

a second staged response circuit comprising a dual AND gate function having signal inputs operably connected to said OR gate and said first staged response signal, and having timing means therein arranged to generate a time delayed signal output in response to a signal input generated by said second staged circuit AND gate means; and

,

at least one additional staged response circuit comprising an AND gate means having signal inputs numerically coinciding with and operably connected to the staged response signals of all preceeding staged response circuits plus said OR gate means signal ouput, and said additional staged response circuits each having timing means arranged to generate a time-delayed output signal after receiving an input signal from said circuit'"'"'s AND gate means;

wherein said second and successive staged response output signals are further adapted to initiate noticeable responses in and around the protected premises in response to the possible intrusion.

2. The deterrence system of claim 1 wherein said additional staged response circuits number at least two and each said staged response circuit timing means includes an adjustable timer.

3. The deterrence system of claim 1 further comprising an automatic reset means for resetting said latch means after a predetermined period of time after said sensors are tripped.

4. The deterence system of claim 3 further comprising manual arming and resetting circuit means adapted to reset said latching means and at least one of said timers, and recycle driver means for generating reset signals to each said circuit timing means.

5. The deterrence system of claim 3 wherein said sensors comprise at least one normally-closed electrical switch having a signal voltage applied thereacross.

6. The deterrence system of claim 5 wherein each said latching means comprises a reset-set bistable element.

7. The deterrence system of claim 1 wherein at least one of said circuit timing means has an additional timer arranged to prevent cascading of signals from one circuit to another.

8. The deterrence system of claim 1 wherein said response circuits are adapted to provide continuing response upon resetting of said latch means even after all but one of said sensors remain tripped.

9. The deterrence system of claim 1 wherein said second and additional staged response circuits each include additional timer means to prevent cascading of a signal through said system, and further to provide staging of said response within predetermined time periods.