Apparatus for generating enhanced/regenerative bracket decode signals

• US 4,642,638 A
• Filed: 06/27/1983
• Issued: 02/10/1987
• Est. Priority Date: 06/27/1983
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Callahan, Patrick O. Jr.
• Primary Examiner(s): Tubbesing, T. H.
• Assistant Examiner(s): Sotomayor, John B.
• Application Number:
  US06/507,658
• Time in Patent Office: 1,324 Days
• Field of Search: 343/6.5 R, 343/6.5 LC, 343/6.8 R, 343/6.8 LC
• US Class Current: 342/45
• CPC Class Codes: G01S 13/784 Coders or decoders therefor; Degarbling systems; Defruiting systems

Abstract

An improved bracket decoder apparatus including an enhanced bracket decoderortion and a regenerative bracket decoder portion operates to generate enhanced bracket decode signals and regenerative bracket decode signals. The foregoing combination of decoder portions will allow digital display systems which use IFF information to detect all targets that are replying regardless of the IFF train spacing, even overlapping replies. The enhanced bracket decoder portion of the apparatus can be operated alone to detect all reply conditions except the one of overlapping replies. The apparatus is configured to provide presently used signals also, i.e., the bracket decode, the degarbled bracket decode, and the range and code information for each video reply.

Claims

1. An apparatus for generating enhanced and regenerative bracket decode signals from IFF composite video, and for detecting the proper number of replies from the IFF composite video regardless of their spacings, comprising:

a first video delay line for receiving and delaying the IFF composite video a predetermined amount;

a second video delay line operatively connected at its input to said first video delay line for additionally delaying the delayed IFF composite video the same predetermined amount;

a third video delay line operatively connected at its input to said second video delay line for still additionally delaying the twice delayed IFF composite video still the same predetermined amount;

a bracket decode AND gate operatively connected at its input to two taps of said second video delay line, the two taps having predetermined delay spacings such that the output of said bracket decode AND gate is a bracket decode signal;

a degarbled bracket decode NOR gate operatively connected at its input to predetermined taps of said first and third video delay lines for generating a "kill junction" signal at its output from the code information at its input;

a degarbled bracket decode AND gate operatively connected at its input to the output of said bracket decode AND gate and said degarbled bracket decode NOR gate for ANDing the bracket decode signal and the "kill junction" signal at its input to product a degarbled bracket decode signal;

an inverter operatively connected to the output of said degarbled bracket decode NOR gate for inverting the "kill junction" signal thereat;

enhanced bracket decode means operatively connected at its input to the output of said inverter and said bracket decode AND gate for generating an enhanced bracket decode signal from the inverted "kill junction" signal and the bracket decode signal; and

regenerative bracket decode means operatively connected at its input to the output of said inverter, said bracket decode AND gate and said enhanced bracket decode means for generating a regenerative bracket decode signal.

2. The apparatus of claim 1 wherein said enhanced bracket decode means comprises:

an enhanced bracket decode AND gate operatively connected at its input to the output of said inverter and said bracket decode AND gate;

a first one shot multivibrator operatively connected at its input to the output of said enhanced bracket decode AND gate and at its inverting output back to the input of said enhanced bracket decode AND gate so as to make said first one shot multivibrator non-retriggerable;

a first delay device operatively connected at its input to the non-inverting output of said first one shot multivibrator so as to allow the enhanced bracket decode signal to be delayed by a predetermined amount so that code/range information can be validated when used in conjunction with the enhanced and regnerative bracket decode signals; and

a second one shot multivibrator operatively connected at its input to the output of said first delay device for detecting the edge of the delayed signal therefrom so as to generate the enhanced bracket decode signal at the non-inverting output of said second one shot multivibrator.

3. The apparatus of claim 2 wherein said regenerative bracket decode means comprises:

a second delay device operative connected to the non-inverting out of said first one shot multivibrator for delaying the signal therefrom a predetermined amount;

a regenerative bracket decode AND gate operatively connected at its input to the output of said inverter, said bracket decode AND gate and said second delay device;

a third one shot multivibrator operatively connected at its input to the output of said regenerative bracket decode AND gate and at its inverting output back to the input of said regenerative bracket decode AND gate so as to make said third one shot multivibrator non-retriggerable;

a fourth one shot multivibrator operatively connected at its input to the non-inverting output of said second one shot multivibrator;

a flip flop logic device operatively connected at its clear input to the non-inverting output of said second one shot multivibrator, at its data input to the inverting output of said fourth one shot multivibrator, and at its clock input to the non-inverting input of said third one shot multivibrator; and

a fifth one shot multivibrator operatively connected at its input to the non-inverting output of said flip flop logic device, said fifth one shot multivibrator being configured to edge detect the signal at its input so as to generate the regenerative bracket decode signal at its non-inverting output.

4. The apparatus of claim 3 further comprising:

a third delay device operatively connected at its input to the output of said bracket decode AND gate for delaying the bracket decode signal therefrom; and

a code/range latch operatively connected at one input to the output of said third delay device, at another input to code information from a predetermined number of taps of said second video delay line, at still another input to a source of IFF range information so as to latch the IFF range information and the code information to make it available as IFF/code range information.

5. The apparatus of claim 4 wherein the predetermined amount, the same predetermined amount, and the still the same predetermined amount of delay for said first, second, and third video delay lines, respectively, is about 21.75 μ

sec.

6. The apparatus of claim 5 wherein the predetermined delay spacings of the taps driving said bracket decode AND gate is about 20.3 μ

sec.

7. The apparatus of claim 6 wherein the pulse width of the pulses at the outputs of said first and third one shot multivibrators is about 20.95 μ

sec.