Epoxy-glass integrated circuit package having bonding pads in a stepped cavity

• US 4,643,935 A
• Filed: 01/21/1986
• Issued: 02/17/1987
• Est. Priority Date: 01/21/1986
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Nagy, Richard A., Norell, Ronald A., McNeal, Norman E.
• Primary Examiner(s): VAN BALEN, WILLIAM
• Application Number:
  US06/819,995
• Time in Patent Office: 392 Days
• Field of Search: 428/77, 428/78, 428/156, 428/157, 428/172, 428/189, 428/190, 428/192, 428/414, 428/417
• US Class Current: 428/157
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 Multilayer substrate
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: Y10T 428/24488 : Differential nonuniformity at margin
• CPC Class Codes: Y10T 428/24612 : Composite web or sheet
• CPC Class Codes: Y10T 428/24752 : Laterally noncoextensive components
• CPC Class Codes: Y10T 428/2476 : Fabric, cloth or textile component
• CPC Class Codes: Y10T 428/31515 : As intermediate layer
• CPC Class Codes: Y10T 428/31525 : Next to glass or quartz

Abstract

An integrated circuit package comprises a plurality of thin flat epoxy-glass layers which are arranged in a stack and are laminated together by prepreg layers that lie between the epoxy-glass layers. This stack has a cavity which is staircase-shaped and extends from an outer epoxy-glass layer to an internal epoxy-glass layer, goes parallel along the internal epoxy-glass layer and then penetrates through it. Patterned electrical conductors lie on the flat surface of the internal epoxy-glass layer, including wire bonding pads on its exposed flat surface portion.

Claims

1. An integrated circuit package comprising:

a plurality of thin flat epoxy-glass layers which are arranged in a stack and are laminated together by prepreg layers that lie between the epoxy-glass layers;

said stack having a cavity which is staircase-shaped and extends from an outer epoxy-glass layer to an internal epoxy-glass layer, and goes parallel along a portion of the flat surface of said internal epoxy-glass layer and then penetrates it; and

patterned electrical conductors on the flat surface of said internal epoxy-glass layer including wire bonding pads on its exposed flat surface portion.

2. An integrated circuit package according to claim 1 wherein said prepreg in said package is blocked from flowing onto said bonding pads while said layers are laminated together by the placement of a thermoplastic plug in said cavity.

3. An integrated circuit package according to claim 1 wherein said prepreg in said package is blocked from flowing onto said bonding pads while said layers are laminated together by an elastic bladder which is stretched and forced into said cavity by a pressurized fluid.

4. An integrated circuit package according to claim 1 wherein said cavity penetrates through multiple internal epoxy-glass layers and exposes respective flat surface portions on each of them, and wherein wire bonding pads are disposed on each of the exposed flat surface portions.

5. An integrated circuit package according to claim 1 wherein wire bonding pads are disposed around said cavity on said outer epoxy-glass layer.

6. An integrated circuit package according to claim 1 wherein said adhesive is at least 0.002 inches thick.

7. An integrated circuit package comprising:

a stack of thin flat first type layers which are made of a fully cured thermosetting resin and are laminated together by second type layers that are made of an adhesive and lie between the first type layers;

said stack having a cavity which extends from an outer first type layer through an internal first type layer and is shaped to expose a portion of the flat surface of said internal first type layer; and

wire bonding pads on said exposed flat surface portion of said internal first type layer.

8. An integrated circuit package according to claim 7 wherein said adhesive layers are selected from an epoxy, triazine, polyimide, teflon, and an acrylic.

9. An integrated circuit package according to claim 7 wherein a fabric is interwoven in said adhesive.

10. An integrated circuit package according to claim 7 wherein said adhesive is at least 0.002 inches thick.

11. An integrated circuit package according to claim 7 wherein said adhesive in said package is blocked from flowing onto said bonding pads while said layers are laminated together by the placement of a thermoplastic plug in said cavity.

12. An integrated circuit package according to claim 7 wherein said adhesive in said package is blocked from flowing onto said bonding pads while said layers are laminated together by an elastic membrane which is stretched and forced into said cavity by a pressurized fluid.