Video memory system
First Claim
1. In a computer system having a raster scan video display, a central processing unit (CPU), and data and address busses coupled to said CPU for transmitting and receiving data to and from specified address locations in said computer system, said address bus including a multiplicity of binary address lines, memory apparatus comprising:
- (1) first memory means, coupled to said address and data busses, for storing program instructions for controlling the operation of said computer system;
(2) second memory means having a data output port, and a multiplicity of addressable memory locations for storing video display data for display on said video display; and
(3) video data acquisition means, coupling said second memory means to said address and data busses, for responding to each of a multiplicity of predefined address signal values asserted on said address bus by said CPU by transmitting corresponding selected portions of the video data in said second memory means to said data bus, including(a) decoder means coupled to said address bus for generating a multiplicity of distinct control signals when said CPU asserts corresponding address signal values on said address bus;
(b) a multiplicity of data fetcher means, each for generating a sequence of address signal values usable for addressing said second memory means, each including(1) video data selection means coupled to said data bus, responsive to predefined ones of said control signals, for selecting a sequence of video address signal values in accordance with data signal values asserted on said data bus by said CPU at the time said control signals are generated; and
(2) video address generating means for generating the next address signal from said sequence of video address signal values each time said decoder means generates a predefined one of said control signals;
(c) video memory address multiplexer means, responsive to the address signal value on a first predefined subset of said binary address lines, for addressing said second memory means using the address signal value generated by the data fetcher means corresponding to the address signal value on said first predefined subset of said binary address lines; and
(d) output logic, coupling said data output port of said second memory means to said data bus, responsive to the address signal on a second predefined subset of said binary address lines, for transmitting the data on said data output port of said second memory means to said data bus in one of multiplicity of predefined formats selected in accordance with the address signal value on said second predefined subset of said binary address lines.
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Accused Products
Abstract
An improved video memory system includes a program memory, a display data memory, and a plurality of data fetchers. The data fetchers are used to indirectly address the display data in the display data memory. The data fetchers are programmed during vertical blanking so that selected display data is fetched at selected vertical display positions. During each scan line each data fetcher is "read" by: (1) decrementing a counter in the data fetcher; (2) comparing the counter value against preselected top and bottom values; and (3) using the counter value to indirectly address display data that is to be displayed on the current scan line if the counter value is between the top and bottom values. This relieves the host computer of having to keep track of the current vertical display position, thereby freeing it to use the saved computer cycles to produce more interesting viedo games with more complex display graphics. In addition there are provided data fetchers that can be programmed to periodically issue signals usable either for drawing a line with a predefined slope or modulating the amplitude of a sound generator.
70 Citations
20 Claims
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1. In a computer system having a raster scan video display, a central processing unit (CPU), and data and address busses coupled to said CPU for transmitting and receiving data to and from specified address locations in said computer system, said address bus including a multiplicity of binary address lines, memory apparatus comprising:
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(1) first memory means, coupled to said address and data busses, for storing program instructions for controlling the operation of said computer system; (2) second memory means having a data output port, and a multiplicity of addressable memory locations for storing video display data for display on said video display; and (3) video data acquisition means, coupling said second memory means to said address and data busses, for responding to each of a multiplicity of predefined address signal values asserted on said address bus by said CPU by transmitting corresponding selected portions of the video data in said second memory means to said data bus, including (a) decoder means coupled to said address bus for generating a multiplicity of distinct control signals when said CPU asserts corresponding address signal values on said address bus; (b) a multiplicity of data fetcher means, each for generating a sequence of address signal values usable for addressing said second memory means, each including (1) video data selection means coupled to said data bus, responsive to predefined ones of said control signals, for selecting a sequence of video address signal values in accordance with data signal values asserted on said data bus by said CPU at the time said control signals are generated; and (2) video address generating means for generating the next address signal from said sequence of video address signal values each time said decoder means generates a predefined one of said control signals; (c) video memory address multiplexer means, responsive to the address signal value on a first predefined subset of said binary address lines, for addressing said second memory means using the address signal value generated by the data fetcher means corresponding to the address signal value on said first predefined subset of said binary address lines; and (d) output logic, coupling said data output port of said second memory means to said data bus, responsive to the address signal on a second predefined subset of said binary address lines, for transmitting the data on said data output port of said second memory means to said data bus in one of multiplicity of predefined formats selected in accordance with the address signal value on said second predefined subset of said binary address lines. - View Dependent Claims (2, 3)
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4. In a computer system having a raster scan video display, a central processing unit (CPU), and data and address busses coupled to said CPU for transmitting and receiving data to and from specified address locations in said computer system, said address bus including a multiplicity of binary address lines, memory apparatus comprising:
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(1) first memory means, coupled to said address and data busses, for storing program instructions for controlling the operation of said computer system; (2) second memory means having a data output port, and a multiplicity of addressable memory locations for storing video display data for display on said video display; and (3) video data acquisition means, coupling said second memory means to said address and data busses, for responding to each of a multiplicity of predefined address signal values asserted on said address bus by said CPU by transmitting corresponding selected portions of the video data in said second memory means to said data bus, including (a) decoder means coupled to said address bus for generating a multiplicity of distinct control signals when said CPU asserts corresponding address signal values on said address bus; (b) a multiplicity of data fetcher means, each for generating a sequence of address signal values usable for addressing said second memory means;
a multiplicity of said data fetcher means each includingflag means for generating a flag signal indicating whether the address signal value generated by said data fetcher means is between two specified address signal values; (c) video memory address multiplexer means, responsive to the address signal value on a first predefined subset of said binary address lines, for addressing said second memory means using the address signal value generated by the data fetcher means corresponding to the address signal value on said first predefined subset of said binary address lines; and (d) output logic means for coupling said data output port of said second memory means to said data bus, including mask means for enabling and disabling the transmission of data from said second memory means to said data bus by logically combining one of said flag signals, selected in accordance the address signal value on said first predefined subset of said binary address lines, with the data from said second memory means. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. For use in a computer system having a raster scan video display, a central processing unit (CPU), and data and address busses coupled to said CPU for transmitting and receiving data to and from specified address locations in said computer system, said address bus including a multiplicity of binary address lines, and memory receptacle means for coupling memory means in a plug-in memory cartridge to said data and address busses,
a plug-in memory cartridge comprising: -
(1) first memory means, coupled to said address and data busses, for storing program instructions for controlling the operation of said computer system; (2) second memory means having a data output port, and a multiplicity of addressable memory locations for storing video display data for display on said video display; (3) video data acquisition means, coupling said second memory means to said address and data busses, for responding to each of a multiplicity of predefined address signal values asserted on said address bus by said CPU by transmitting corresponding selected portions of the video data in said second memory means to said data bus, including (a) decoder means coupled to said address bus for generating a multiplicity of distinct control signals when said CPU asserts corresponding address signal values on said address bus; (b) a multiplicity of data fetcher means, each for generating a sequence of address signal values usable for addressing said second memory means, each including (1) video data selection means coupled to said data bus, responsive to predefined ones of said control signals, for selecting a sequence of video address signal values in accordance with data signal values asserted on said data bus by said CPU at the time said control signals are generated; and (2) video address generating means for generating the next address signal from said sequence of video address signal values each time said decoder means generates a predefined one of said control signals; (c) video memory address multiplexer means, responsive to the address signal value on a first predefined subset of said binary address lines, for addressing said second memory means using the address signal value generated by the data fetcher means corresponding to the address signal value on said first predefined subset of said binary address lines; and (d) output logic, coupling said data output port of said second memory means to said data bus; and (4) a cartridge housing, compatible with said computer system'"'"'s memory receptacle means, for holding said first and second memory means and said video data acquisition means. - View Dependent Claims (17, 18, 19, 20)
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Specification