High-speed switching processor for a burst-switching communications system

• US 4,644,529 A
• Filed: 08/02/1985
• Issued: 02/17/1987
• Est. Priority Date: 08/02/1985
• Status: Expired due to Term

• Current Assignee: GTE Laboratories Incorporated (Lumen Technologies, Inc.)
• Original Assignee: GTE Laboratories Incorporated (Lumen Technologies, Inc.)
• Inventors: Rao, Pamidimukkala M. V., Eliscu, Mark, Amstutz, Stanford R.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Rokoff, Kenneth I.
• Application Number:
  US06/762,592
• Time in Patent Office: 564 Days
• Field of Search: 370/58, 370/60, 370/94, 370/110.1, 179/18 ES
• US Class Current: 370/422
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

This invention provides a high-speed switching processor which may be employed as a component of a link switch or a hub switch in a burst-switching communications system. When so employed, transmission speeds for integrated voice and data services over communications links between switches may be equivalent to the T1 rate or higher. A burst is a plurality of bytes which represents, for example, a block of data or a spurt of voice energy sensed by silence/voice detectors located at voice ports. In a preferred embodiment, the architecture of the switching processor includes a data/address bus, control including a stored program in a 64-bit wide PROM, a finite-state machine having character and channel states for generating a jump address in the stored program based on the status of an incoming burst, interfaces with other components of the switch such as the queue sequencer, a companion processor, and a dual-port RAM for generating a buffer address as a function of channel number for the dynamic buffer in character memory in which the incoming burst is being stored. In this architecture, most components of the switching processor operate substantially in parallel with and independently of the control which is a contributing factor to the overall speed advantage realized by the switching processor. With software or firmware variations, the switching processor may be employed as several different components of a link or hub switch.

Claims

1. A high-speed switching processor for use in a switch of a burst-switching communications system, a burst being a plurality of bytes, said system including a plurality of switches interconnected by time-division multiplexed communications links, each link having a plurality of frames within each second of time, each frame having a plurality of channels, each channel having communications capacity for the transmission of one byte, a byte being a predetermined number of bits, a bit being one binary digit, said system including a plurality of ports, each port being a component of a switch, said switch including at least one switching processor, a queue sequencer, a character memory, and a channel clock, said character memory and queue sequencer each having a respective bus coupled therewith, said switching processor comprising:

(a) a data/address bus;

(b) control means coupled with said data/address bus for controlling said switching processor, said control means including stored-program memory and execution means, said control means having means for receiving and being responsive to a signal from said channel clock;

(c) jump-address means coupled with said data/address bus and said control means, for generating a jump address based on character-state and channel-state and for transmitting said jump address to said control means, said jump-address means operating substantially in parallel with and independently of said control means;

(d) external-interface means coupled with said data/address bus for providing an interface between said switching processor and said communications links and ports, said external-interface means having the ability to receive a byte in the current channel from a communication link or port, said external-interface means operating substantially in parallel with and independently of said control means;

(e) character-memory interface means coupled with said data/address bus for providing an interface between said switching processor and said character memory, said character-memory interface means having the ability to read or write a byte from said character memory, said character-interface means operating substantially in parallel with and independently of said control means;

(f) queue-sequencer interface means coupled with said data/address bus for providing an interface between said switching processor and said queue sequencer, said queue-sequencer interface means having the ability to receive a buffer address from the queue sequencer, said queue-sequencer interface means operating substantially in parallel with and independently of said control means and said queue sequencer; and

(g) buffer-address means coupled between said queue-sequencer interface means and said character-memory interface means for generating a buffer address based on the channel number, said buffer-address means having the ability to receive said buffer address from said queue-sequencer interface means, said buffer address means operating substantially in parallel with and independently of said control means;

(h) said jump-address means being coupled with said external-interface means and having the ability to receive a byte of a burst from said external-interface means;

(i) said control means having the ability to receive said jump address from said jump-address means and to transfer processing control to the instruction in said stored-program memory located at the address indicated by said jump address.

2. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein the transmission speeds over said communications links are substantially equivalent to the T1 rate or a higher rate.

3. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein a byte is eight bits.

4. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 3 wherein said jump-address means comprises a finite-state machine having character states and channel states.

5. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 4 wherein said character states of said finite state machine comprise clear, flag-found, and data-link escape found.

6. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 5 wherein said channel states of said finite state machine comprise await first header byte, await second header byte, await third header byte, await fourth header byte, process burst, abort burst, await termination sequence, and process control burst.

7. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein said buffer-address means includes a dual-port random-access memory.

8. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein said stored-program memory is a programmable read-only memory having a word length of at least sixty-four bits.

9. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein said system includes a link switch and said switching processor is at least one component of said link switch.

10. A high-speed switching processor for use in a switch of a burst-switching communications system as described in claim 1 wherein said communications system includes a hub switch and said switching processor is at least one component of said hub switch.

11. A high-speed switching processor for use in a link switch of a burst-switching communications system, a burst being a plurality of bytes, a byte being a predetermined number of bits, a bit being one binary digit, said system including a link switch having a plurality of ports, each port being a component of said switch, each port being associated with a communications channel, said link switch including at least one switching processor, a queue sequencer, a character memory, and a channel clock, said character memory and queue sequencer each having a respective bus coupled therewith, said switching processor comprising:

(a) a data/address bus;

(b) control means coupled with said data/address bus for controlling said switching processor, said control means including stored-program memory and execution means, said control means having means for receiving and being responsive to a signal from said channel clock;

(c) jump-address means coupled with said data/address bus and said control means, for generating a jump address based on character-state and channel-state and for transmitting said jump address to said control means, said jump-address means operating substantially in parallel with and independently of said control means;

(d) external-interface means coupled with said data/address bus for providing an interface between said switching processor and said ports, said external-interface means having the ability to receive a byte in the current communications channel, said external-interface means operating substantially in parallel with and independently of said control means;

(e) character-memory interface means coupled with said data/address bus for providing an interface between said switching processor and said character memory, said character-memory interface means having the ability to read or write a byte from said character memory, said character-interface means operating substantially in parallel with and independently of said control means;

(f) queue-sequencer interface means coupled with said data/address bus for providing an interface between said switching processor and said queue sequencer, said queue-sequencer interface means having the ability to receive a buffer address from the queue sequencer, said queue-sequencer interface means operating substantially in parallel with and independently of said control means and said queue sequencer; and

(g) buffer-address means coupled between said queue-sequencer interface means and said character-memory interface means for generating a buffer address based on the channel number, said buffer-address means having the ability to receive said buffer address from said queue-sequencer interface means, said buffer address means operating substantially in parallel with and independently of said control means;

(h) said jump-address means being coupled with said external-interface means and having the ability to receive a byte of a burst from said external-interface means;

(i) said control means having the ability to receive said jump address from said jump-address means and to transfer processing control to the instruction in said stored-program memory located at the address indicated by said jump address.

12. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 11 wherein a byte is eight bits.

13. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 12 wherein said jump-address means comprises a finite-state machine having character states and channel states.

14. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 13 wherein said character states of said finite state machine comprise clear, flag-found, and data-link escape found.

15. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 14 wherein said channel states of said finite state machine comprise await first header byte, await second header byte, await third header byte, await fourth header byte, process burst, abort burst, await termination sequence, and process control burst.

16. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 11 wherein said buffer-address means includes a dual-port random-access memory.

17. A high-speed switching processor for use in a link switch of a burst-switching communications system as described in claim 11 wherein said stored-program memory is a programmable read-only memory having a word length of at least sixty-four bits.