Intranetwork code division multiple access communication system

• US 4,644,560 A
• Filed: 03/21/1985
• Issued: 02/17/1987
• Est. Priority Date: 08/13/1982
• Status: Expired due to Term

• Current Assignee: Hazeltine Corporation (BAE Systems Plc)
• Original Assignee: Hazeltine Corporation (BAE Systems Plc)
• Inventors: Courtien, John F., Torre, Frank M.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/714,296
• Time in Patent Office: 698 Days
• Field of Search: 375/1, 375/2.1, 178/22.01, 178/22.17, 455/26, 455/31, 455/32, 455/38, 370/18, 370/91, 370/92, 370/93, 370/95, 370/96
• US Class Current: 370/342
• CPC Class Codes: H04B 1/7073 Synchronisation aspects
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04J 13/16 Code allocation

Abstract

A CDMA format is used within a network to permit communication between members of a network. Network members are synchronized to each other and are each aware of a predetermined set of code words which has been established. A member desiring to transmit data selects a code word from the predetermined set. If there are unused code words, one of the unused words is randomly selected. If all words are being used, the code word of the farthest user is selected. Since all members are synchronized in time to stable clocks, the range of each user is known. All members of the network are always listening and keeping track of detections of other users and code words. Transmitted signals are a series of pulses with a jitter or sync pulse inserted within each series. The number and location of sync pulses is unique for each code and defines the CDMA code of the signal. A pseudorandom noise generator synchronized to the clock is gated with coded data pulsed with appropriate jitter insertion and transmitted over a frequency determined by the pseudorandom number at any instant in time.

Claims

1. An apparatus for transmitting digital data within a network made up of a plurality of the appratus, said apparatus comprising:

a clock;

first means for coding the digital data to be transmitted;

second means for monitoring the transmissions within the network and for determining unused code words;

third means for selecting a code word from the set of unused code words determined by said second means;

fourth means for defining a carrier frequency, a jitter-insertion timing delay and a phase based on the code word selected by said third means, said fourth means synchronized to the clock;

fifth means for generating a representative signal representing the digital data having a phase corresponding to the phase defined by the fourth means and having a sync pulse with a timing delay corresponding to the timing delay defined by the fourth means, and for modulating the respresentative signal onto the carrier signal; and

sixth means for transmitting the modulated carrier signal.

2. The apparatus of claim 1 wherein said second means for monitoring comprises:

an acquistition matched filter for filtering any incoming signals, said acquisition filter controlled by said fourth means and matched to the codes of the predetermined set;

means for detecting the codes embodied in output signals provided by the matched filter;

means for demodulating including a message matched filter responsive to the fourth means, and for filtering the incoming signal in response to the means for detecting; and

means for decoding the demodulated data.

3. The apparatus of claim 2 wherein said third means comprises a source selection processor including a look-up table for defining a code word to be used and assigning the selected code word.

4. The apparatus of claim 3 wherein said fourth means comprises a transec generator including:

a pseudorandom noise generator providing psuedorandom noise as the phase information to be combined with the coded digital data provided by the first means;

first and second programmable counters responsive to the source selection processor for defining the timing delay and the carrier signal; and

a jitter insertion processor for adjusting the sync pulse location of the representative signal in response to the first counter, said jitter insertion processor including a look-up table defining the successive jitter intervals.

5. The apparatus of claim 4 wherein said fifth means comprises a signal generator including:

means for gating the pseudorandom noise with the coded digital data;

means for delaying the gated data in response to the timing delay provided by the trasec generator;

a frequency synthesizer responsive to the transec generator for generating the carrier signal;

means for mixing the delayed, gated data with the carrier signal.

6. The apparatus of claim 5 wherein said means for detecting comprises:

a pulse splitter for determining the centroid of pulses provided by the acquisition filter; and

a signal detector for evaluating successive pulses and indicating when such pulses correspond to a coded signal.

7. The apparatus of claim 6 wherein said signal detector comprises a dejitter processor for detecting jitter pulses in the pulse splitter output and for generating decoding information and binary integration information responsive to the pulse splitter output which is provided to the source selection processor.

8. The apparatus of claim 7 further including a look-up table defining successive sync intervals for each instant in time as specified by the clock.