Superposed quadrature modulated baseband signal processor

• US 4,644,565 A
• Filed: 06/12/1984
• Issued: 02/17/1987
• Est. Priority Date: 06/12/1984
• Status: Expired due to Term

• Current Assignee: Kamilo Feher
• Original Assignee: Canadian Patents and Development Limited
• Inventors: Feher, Kamilo, Seo, Jongsoo
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/619,740
• Time in Patent Office: 980 Days
• Field of Search: 375/18, 375/37, 375/38, 375/39, 375/43, 375/60, 375/58, 375/56, 375/84, 375/85, 364/718, 364/721, 360/45, 178/69 N, 307/260, 307/261, 328/27, 328/34, 343/17.1 R, 332/9 R, 332/37 R, 332/10
• US Class Current: 375/296
• CPC Class Codes: H04L 25/03834 using pulse shaping
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

A signal processor for providing a continuous raised cosine output signal having no jitter or intersymbol-interference and with controllable main and side lobes. An NRZ input signal is converted to a double interval raised cosine pulse signal having an amplitude normalized to 1.0. Another single interval raised cosine pulse signal having a peak amplitude (A-1) is superposed with the former raised cosine pulse to provide the output signal.

Claims

1. A signal processor comprising:

(a) means for converting an NRZ input signal to a double interval raised cosine pulse having a peak amplitude normalized to 1.0,

(b) means for superposing another weighted single interval raised cosine pulse having a peak amplitude (A-1) with the former raised cosine pulse to provide a continuous output signal, of a form related to the NRZ input signal,

in which the converting and superposing means are comprised of;

(i) means for detecting the binary values of each pair of consecutive bits of the NRZ input signal;

(ii) means for generating an output signal having the function Y₁ =-A(1-A) cos (2π

t/T) if the pair of bits are -1, -1;

(iii) means for generating an output signal having the function Y₂ =-cos (π

t/T) if the pair of bits are 1, -1;

(iv) means for generating an output signal having the function Y₃ =cos (π

t/T) if the pair of bits are -1, 1 and

(v) means for generating an output signal having the function Y₄ =A+(1-A) cos (2π

t/T) if the pair of bits are 1,1,

where T is the NRZ input signal symbol duration, and A is the amplitude parameter of the processor,

the output signals being continuous.

2. A signal processor as defined in claim 1 in which the converting and superposing means is comprised of means for overlapping shaped pulses to form the said output signal functions.

3. A signal processor as defined in claim 1 constituting a filter.

4. A signal processor as defined in claim 1 for providing a signal to a modulator.

5. A signal process for a modulator comprising:

(a) means for detecting the binary values of each pair of consecutive bits of an NRZ input signal,

(b) means for generating signals having waveshapes according to the functions y₁ =-A-(1-A) cos (2π

t/T), y₂ =-cos (π

t/T), y₃ =cos (π

t/T) and y₄ =A+(1-A) cos (2t/T), where T is the input signal symbol duration, and A is an amplitude parameter,

(c) means for switching said y₁, y₂, y₃ and y₄ signals to an output transmission path to form a continuous signal according to the following table;

space="preserve" listing-type="tabular">______________________________________ 1st NRZ bit Following NRZ bit Output Signal ______________________________________ -1 -1 y.sub.1 1 -1 y.sub.2 -1 1 y.sub.3 1 1 y.sub.4 ______________________________________

6. A signal processor as defined in claim 5, including a four channel multiplexer, means for applying said signals y₁, y₂, y₃ and y₄ to separate signal inputs of the multiplexer, means for generating control signals from the detected binary values of the pairs of consecutive bits, and for applying the control signals to control inputs of the multiplexer to cause the multiplexer to switch any of the signals at its separate signal inputs to be connected to its output transmission path according to said table.

7. A processor as defined in claim 6, in which the signal generating means is comprised of a pair of cosine function generators, the output of one of said generators being connected through an amplifier having amplification factor A, the outputs of the second of said generators and of the amplifier providing signals having the functions y₂ and y₁ respectively, and the outputs of said second generator and of the amplifier being connected through inverters to provide signals having the functions y₃ and y₄ respectively.

8. A processor as defined in claim 6, including a source of clock pulses having the same bit rate as the NRZ input signal, the generating means being formed of a pair of bandpass filters for translating the clock pulses into cosine functions, the output of one of said bandpass filters being connected through an amplifier having amplification factor A, the outputs of the second of said bandpass filters and of the amplifier providing signals having the functions y₂ and y₁ respectively, and the outputs of said second bandpass filter and of the amplifier being connected through inverters to provide signals having the functions y₃ and y₄ respectively.

9. A processor as defined in claim 6 in which the parameter A is adjustable to control the bandwidth of the main spectral lobe and the side lobe roll-off characteristics of the signal on the output transmission path.

10. A processor as defined in claim 9, in which the signal generating means is comprised of a pair of cosine function generators, the output of one of said generators being connected through an amplifier having amplification factor A, the outputs of the second of said generators and of the amplifier providing signals having the functions y₂ and y₁ respectively, and the outputs of said second generator and of the amplifier being connected through inverters to provide signals having the functions y₃ and y₄ respectively.

11. A processor as defined in claim 9, including a source of clock pulses having the same bit rate as the NRZ input signal, the generating means being formed of a pair of bandpass filters for translating the clock pulses into cosine functions, the output of one of said bandpass filters being connected through an amplifier having amplification factor A, the outputs of the second of said bandpass filters and of the amplifier providing signals having the functions y₂ and y₁ respectively, and the outputs of said second bandpass filter and of the amplifier being connected through inverters to provide signals having the functions y₃ and y₄ respectively.

12. A processor as defined in claim 5, in which the signal generating means is comprised of a pair of cosine function generators, the output of one of said generators being connected through an amplifier having amplification factor A, the outputs of the second of said generators and of the amplifier providing signals having the functions y₂ and y₁ respectively, and the outputs of said second generator and of the amplifier being connected through inverters to provide signals having the functions y₃ and y₄ respectively.

13. A processor as defined in claim 5, including a source of clock pulses having the same bit rate as the NRZ input signal, the generating means being formed of a pair of bandpass filters for translating the clock pulses into cosine functions, the output of one of said bandpass filters being connected through an amplifier having amplification factor A, the outputs of the second of said bandpass filters and of the amplifier providing signals having the functions y₂ and y₁ respectively, and the outputs of said second bandpass filter and of the amplifier being connected through inverters to provide signals having the functions y₃ and y₄ respectively.

14. A signal processor as defined in claim 5 constituting a filter.

15. A signal process or as defined in claim 5 for providing a signal to a modulator.

16. A modulator comprising:

(a) a pair of signal processors as defined in claim 5,

(b) a source of NRZ data signals,

(c) means for applying the data signals to one of the signal processors,

(d) means for delaying the data signals by one bit period and applying the delayed data signals to the other signal processor,

(e) means for combining an output signal from the first signal processor with a carrier signal,

(f) means for combining an output signal from the other signal processor with the carrier signal shifted 90°

,

(g) means for summing the combined output signals to provide a modulated output signal.

17. A signal processor comprising:

(a) means for detecting the binary values of each pair of consecutive bits of a digital signal,

(b) means for generating a continuous output signal having a waveshape dependent on the binary values of each pair of said bits,

in which said continuous output signal is formed of waveshapes according to the functions Y₁ =-A-(1-A) cos (2π

t/T), Y₂ =-cos (π

t/T), Y₃ =cos (π

t/T) and Y₄ =A+(1-A) cos (2π

t/T) where T is the input signal symbol duration, and A is an amplitude parameter, which follow in smooth sequence according to the following table;

space="preserve" listing-type="tabular">______________________________________ 1st NRZ bit Following NRZ bit Output Signal ______________________________________ -1 -1 Y.sub.1 1 -1 Y.sub.2 -1 1 Y.sub.3 1 1 Y.sub.4 ______________________________________

18. A signal processor as defined in claim 17 in which the generating means is comprised of means for overlapping shaped pulses to form the said output signal.

19. A signal processor as defined in claim 17 constituting a filter.

20. A signal processor as defined in claim 17 for providing a signal to a modulator.