Semiconductor device

• US 4,646,126 A
• Filed: 08/08/1984
• Issued: 02/24/1987
• Est. Priority Date: 10/07/1983
• Status: Expired due to Term

• Current Assignee: Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iizuka, Tetsuya
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/638,782
• Time in Patent Office: 930 Days
• Field of Search: 357/68, 357/71, 357/80, 357/65, 357/51, 357/71 P, 357/75, 357/73, 357/81
• US Class Current: 257/296
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/4823 connecting the wire to a pin of the item
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2224/85424 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/4926 the materials containing semiconductor material
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Disclosed is a semiconductor device in which IC chips, tested and evaluated as good, are mounted on a silicon substrate, and interconnection wiring layers and pads for IC chips are provided on the substrate with an insulation film interposed therebetween.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

an IC chip mounted directly on a first region of said substrate;

a first insulation film formed on said substrate, said first insulation film having one region thinner than any other region;

an interconnection wiring layer serving as a power line formed on said one region of said first insulation film, said first insulation film and said interconnection wiring layer and said substrate forming a capacitor to serve as a filter for reducing noise coming from said power line;

a second insulation film formed on said interconnection wiring layer;

a conductive bonding layer for forming an electrical connection for said IC chip, said conductive bonding layer being formed on said second insulation film above said interconnection wiring layer; and

means for connecting said IC chip and said conductive bonding layer.

2. A semiconductor device according to claim 1, in which said interconnection wiring layer is made of polycrystalline silicon.

3. A semiconductor device according to claim 1, in which said interconnection wiring layer is made of aluminum.

5. A semiconductor device according to claim 1, in which said substrate is made of silicon.

6. A semiconductor device according to claim 5, in which said substrate has a high impurity concentration.

4. A semiconductor device comprising:

a semiconductor substrate;

an IC chip mounted directly on a first region of said substrate;

a first insulation film formed on said substrate, said first insulation film having one region thinner than any other region;

an interconnection wiring layer, located in close proximity to said first region of said substrate wherein said IC chip is placed, said interconnection wiring layer serving as a power line formed on said one region of said first insulation film, said first insulation film and said interconnection wiring layer and said substrate forming a capacitor to serve as a filter for reducing noise coming from said power line;

a second insulation film formed on said interconnection wiring layer;

a conductive bonding layer for forming an electrical connection for said IC chip, said conductive bonding layer being formed on said second insulation film above said interconnection wiring layer; and

means for connecting said IC chip and said conductive bonding layer.

7. A semiconductor device according to claim 4, in which substrate has a high impurity concentration.

8. A semiconductor device according to claim 4, in which said substrate is made of silicon.

9. A semiconductor device according to claim 4, in which said interconnection wiring layer is made of polycrystalline silicon.

10. A semiconductor device according to claim 4, in which said interconnection wiring layer is made of aluminum.