High-density electronic processing package--structure and fabrication

• US 4,646,128 A
• Filed: 04/08/1985
• Issued: 02/24/1987
• Est. Priority Date: 09/16/1980
• Status: Expired due to Term

• Current Assignee: Irvine Sensors Corp.
• Original Assignee: Irvine Sensors Corp.
• Inventors: Carson, John C., Clark, Stewart A.
• Primary Examiner(s): Davie, James W.
• Application Number:
  US06/720,902
• Time in Patent Office: 687 Days
• Field of Search: 174/68.5, 250/332, 250/370 G, 250/578, 357/56, 357/75, 357/74, 361/396, 361/414
• US Class Current: 257/777
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/042 the devices being arranged next to each other solar cells H01L31/042
• CPC Class Codes: H01L 25/043 Stacked arrangements of devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high-density electronic package module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of thin film circuitry on the access ends, each access plane is etched to cut back the semiconductor material then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Claims

1. A high-density electronic package comprising:

a plurality of integrated-circuit-providing semiconductor substrates of substantially identical dimensions stacked and secured together to form a multiple layer structure having the shape of a rectangular parallelepiped, at least one surface of which provides an access plane end perpendicular to the planes of the layers;

the access plane end of each substrate having a multiplicity of closely-spaced elecrical contact points provided by the ends of the metal leads formed as part of the integrated circuitry on the substrate;

insulation layers between adjacent substrates to insulate the body of each substrate from adjacent substrates in the stack; and

insulation covering the entire access plane end of the stacked substrates except for the contact points thereon, and so formed as to prevent current leakage between the contact points and the access plane ends of the substrates;

the electrical contact points on the access plane ends of the stacked substrates extending through the insulation in order to be individually accessible for contact with electrical conductors external to the stacked substrates.

2. The high-density electronic package of claim 1 wherein the access plane end of the stacked substrates is prepared by a method including the following steps:

etching the access plane to remove a thin layer of semiconductor substrate material without affecting the electrical contact points on the access plane;

applying insulation material to cover the etched surface; and

removing sufficient insulation material from the surface to uncover the electrical contact points.

3. The high-density electronic package of claim 2 wherein the step of etching the access plane is accomplished by a dry process using a gas plasma.

4. The high-density electronic package of claim 2 wherein the insulation material is a material which is applied in liquid form and then cured.

5. The high-density electronic package of claim 4 wherein the insulation material is a curable liquid polymer which is spun on and then cured.

6. The high-density electronic package of claim 5 wherein the insulation material is polyimide.

7. The high-density electronic package of claim 3 wherein the insulation material is a curable liquid polymer which is applied and then cured.

8. A high-density electronic package comprising:

a plurality of integrated-circuit-providing semiconductor substrates of substantially identical dimensions stacked and secured together to form a multiple layer structure, at least one end of which terminates in an access plane end perpendicular to the planes of the layers;

the access plane end of each substrate having a multiplicity of closely-spaced electrical contact points provided by the ends of the metal leads formed as part of the integrated circuitry on the substrate;

insulation layers between adjacent substrates to insulate the body of each substrate from adjacent substrates in the stack;

10. The high-density electronic package of claim 8 wherein the access plane end of the stacked substrates is prepared by a method including the following steps:

etching the access plane to remove a thin layer of semiconductor substrate material without affecting the electrical contact points on the access plane;

applying insulation material to cover the etched surface; and

removing sufficient insulation material from the surface to uncover the electrical contact points.

15. The high-density electronic package of claim 10 wherein the insulation material is a curable liquid polymer which is applied and then cured.

9. insulation covering the entire access plane end of the stacked substrates except for the contact points thereon, and so formed as to prevent current leakage between the contact points and the access plane ends of the substrates;

the electrical contact points on the access plane ends of the stacked substrates extending through the insulation in order to be individually accessible for contact with electrical conductors external to the stacked substrates; and

thin film metallization on the access plane end to make electrical contact with the multiplicity of contact points provided by the leads formed as part of the integrated circuitry on the substrates.

11. The high-density electronic package of claim 9 wherein the step of etching the access plane is accomplished by a dry process using a gas plasma.

12. The high-density electronic package of claim 9 wherein the insulation material is a material which is applied in liquid form and then cured.

13. The high-density electronic package of claim 11 wherein the insulation material is a curable liquid polymer which is spun on and then cured.

14. The high-density electronic package of claim 12 wherein the insulation material is polyimide.