Computer graphics, parametric patch parallel subdivision processor

• US 4,646,251 A
• Filed: 10/03/1985
• Issued: 02/24/1987
• Est. Priority Date: 10/03/1985
• Status: Expired due to Fees

• Current Assignee: PTC Inc.
• Original Assignee: Evans & Sutherland Computer Corp. (Elevate Entertainment, Inc.)
• Inventors: Jensen, Thomas W., Hayes, Alan B., Madsen, Bruce K., Brown, Russell A.
• Primary Examiner(s): Gellner, Michael L.
• Application Number:
  US06/783,492
• Time in Patent Office: 509 Days
• Field of Search: 364/518, 364/521, 364/522
• US Class Current: 345/423
• CPC Class Codes: G06T 17/20 Finite element generation, e.g. wire-frame surface description, tesselation

Abstract

A system is disclosed for subdividing parametric patches for use in a computer graphics system to develop images. The system utilizes initial data, provided as by an interactive user, to represent control points for an initial patch from which the system rapidly computes control points for subpatches using parallel processors. The disclosed system is recursive so that each level of subdivision leads to greater refinement of an initial patch. In one embodiment, the processors in the system compute multiple control points, the grouping of processors exploiting patch symmetrical properties.

Claims

1. A system for subdividing parametric patches defined by initial control points to attain control points for subpatches in accordance with established subdivision equations, comprising:

means for supplying signals representative of said initial control points for a patch to be subdivided;

a plurality of processors for executing said subdivision equations connected to receive said signals representative of said initial control points for a patch to be subdivided;

means for controlling said processors to selectively process said signals representative of said initial control points to provide resultant signals representative of control points for subpatches; and

means for receiving said resultant signals from said processors.

2. A system according to claim 1 wherein said means for supplying signals comprises bus means for supplying said signals representative of said initial control points in sequence for selective use by said processors.

3. A system according to claim 2 wherein said means for receiving said resultant signals comprises a means for passing said resultant signals in sequence.

4. A system according to claim 1 wherein said plurality of processors comprises a processor for each of said control points for subpatches to be generated.

5. A system according to claim 1 wherein said plurality of processors comprise less than one processor for each of said control points for subpatches and wherein certain of said processors include structure for computing a plurality of said control points for subpatches.

6. A system according to claim 1 wherein said plurality of processors each comprise substantially similar structures each for generating a plurality of said control points for subpatches.

7. A system according to claim 1 wherein said means for supplying signals representative of said initial control points includes means for providing signals representative of a name for said initial control points and means for providing signals representative of the value of data for said initial control points.

8. A system according to claim 1 wherein said processors include logic means for selectively accepting said signals representative of said initial control points.

9. A system according to claim 8 wherein said logic means includes a counter.

10. A system according to claim 1 wherein said means for supplying signals comprises bus means for supplying said signals representative of said initial control points in sequence for selective use by said processors and wherein said means for receiving said resultant signals comprises a means for passing said resultant signals in sequence.

11. A system according to claim 10 wherein said plurality of processors comprises less than one processor for each of said control points and wherein certain of said processors include structure for computing a plurality of said control points for subpatches.

12. A system according to claim 10 further including control means to subdivide space curves.

13. A system according to claim 1 wherein said means for receiving resultant signals representative of control points for subpatches includes means for providing signals representative of a name for said control points for subpatches and means for receiving signals representative of the value of data for said control points for subpatches.

14. A system according to claim 1 wherein said processors include logic means for selectively transmitting said signals representative of said control points for subpatches.

15. A system according to claim 14 wherein said logic means includes a counter.

16. A system according to claim 1 wherein said means for controlling includes a RAM.

17. A system according to claim 1 wherein said means for controlling includes a PLA.

18. A system according to claim 1 wherein said processors comprise multiple groups of processors and said groups are substantially identical.

19. A system according to claim 1 wherein processors comprise a single group of processors and wherein said means for supplying signals comprises means for repeatedly supplying said initial control points whereby upon each such supplying, said processors compute a different set of control points for subpatches.