Programmable semiconductor structures and methods for using the same

• US 4,646,266 A
• Filed: 09/28/1984
• Issued: 02/24/1987
• Est. Priority Date: 09/28/1984
• Status: Expired due to Term

• Current Assignee: Energy Conversion Devices
• Original Assignee: Energy Conversion Devices
• Inventors: Yaniv, Zvi, Ovshinsky, Stanford R., Johnson, Robert R., Cannella, Vincent D.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/655,961
• Time in Patent Office: 879 Days
• Field of Search: 365/94, 365/96, 365/103, 365/104, 365/105, 365/45, 365/113, 365/163, 365/168, 357/45, 357/59, 357/86, 340/825.83, 340/825.84, 307/465
• US Class Current: 365/105
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: Y10S 257/926 Elongated lead extending axially through another elongated lead

Abstract

A solid state semiconductor device is disclosed which is programmable so as to alter the impedance between its two terminals. In many embodiments, the device is programmable to have any one of four conditions: a first in which the electrical impedance is relatively high in both directions; a second in which the impedance is relatively high in one direction and relatively low in the opposite direction; a third in which the impedance is relatively high in the opposite direction and relatively low in the first direction; and a fourth in which the impedance is relatively low in both directions. Such a programmable device can be made with semiconductor layers which form two series coupled back-to-back diodes, each of which can be selectively programmed to lose its rectifying feature. Structures are disclosed which include a plurality of such programmable devices in one or more separately programmable planes, each with its own addressing means. Programmable logic arrays can be formed out of such multilayered cell structures, including programmable logic arrays, in which the AND and OR planes are vertically disposed one on top of the other.

Claims

1. A solid state semiconductor device having at least two terminals and a plurality of layers of semiconductor material to provide a plurality of interacting semiconductor functions, said device being programmable in a first condition in which the electrical impedance between said two terminals is relatively high in both directions, a second condition in which the electrical impedance between said two terminals is relatively high in one direction and relatively low in the opposite direction, a third condition in which the electrical impedance between said two terminals is relatively high in said opposite direction and relatively low in said one direction, and a fourth condition in which the electrical impedance between said two terminals is relatively low in both said directions.

2. A device as defined in claim 1, wherein said device is manufactured in one of said conditions and programmable into any one of said remaining three conditions.

3. A device as defined in claim 2, wherein said device is manufactured in said first condition.

4. A device as defined in claim 1, wherein said device includes at least one layer of phase-changeable material.

5. A device as defined in claim 4, wherein said phase-changeable material comprises an amorphous semiconductor alloy.

6. A device as defined in claim 5, wherein said amorphous semiconductor alloy includes silicon.

7. A device as defined in claim 5, wherein said amorphous semiconductor alloy includes germanium.

8. A device as defined in claim 5, wherein said amorphous semiconductor alloy includes both silicon and germanium.

9. A device as defined in claim 1 wherein said plurality of layers of semiconductor material form a pair of series coupled back-to-back diodes for providing said interacting semiconductor functions.

10. A device as defined in claim 9 including metal between said back-to-back diodes.

11. A device as defined in claim 1, wherein said device has at least two interacting semiconductor functions and wherein said device further includes a third terminal for separately accessing at least one of said semiconductor functions between said third terminal and a first of said two terminals and at least one other of said semiconductor functions between said third terminal and the other of said two terminals.

12. A solid state semiconductor cell structure having at least two terminal planes and a plurality of layers of semiconductor material to provide a plurality of interacting semiconductor functions, said cell structure being programmable in a first condition in which the electrical impedance between said two planes is relatively high in both directions, a second condition in which the electrical impedance between said two planes is relatively high in one direction and relatively low in the opposite direction, a third condition in which the electrical impedance between said two planes is relatively high in said opposite direction and relatively low in said one direction, and a fourth condition in which the electrical impedance between said two planes is relatively low in both said directions, and

addressing means for programming said cell structure at unique selected locations thereof into any one of said conditions.

13. A cell structure as defined in claim 12, wherein said addressing means comprises a first plurality of spaced apart address lines on one of said terminal planes and a second plurality of spaced apart address lines on said other terminal plane crossing said first plurality of address lines at an angle to form a plurality of crossover points defining said unique selected locations.

14. A cell structure as defined in claim 12, wherein said cell structure is manufactured in one of said conditions and programmable at said unique selected locations into any one of said remaining three conditions.

15. A cell structure as defined in claim 14, wherein said cell structure is manufactured in said first condition.

16. A cell structure as defined in claim 12, wherein said cell structure includes at least one layer of phase changeable material.

17. A cell structure as defined in claim 16, wherein said phase changeable material comprises an amorphous semiconductor alloy.

18. A cell structure as defined in claim 17, wherein said amorphous semiconductor alloy includes silicon.

19. A cell structure as defined in claim 17, wherein said amorphous semiconductor alloy includes germanium.

20. A cell structure as defined in claim 17, wherein said amorphous semiconductor alloy includes silicon and germanium.

21. A cell structure as defined in claim 12 wherein said plurality of layers of semiconductor material form a pair of series coupled back-to-back diodes for providing said interacting semiconductor functions.

22. A cell structure as defined in claim 21 including metal between said back-to-back diodes.

23. A cell structure as defined in claim 12, wherein said cell structure has at least two interacting semiconductor functions and wherein said cell structure further includes a third terminal plane for separately accessing at least one of said semiconductor functions between said third terminal plane and a first of said two terminal planes and at least one other of said semiconductor functions between said third terminal plane and the other of said two terminal planes.

24. A programmable cell structure comprising a first plurality of vertically arrayed layers of semiconductor materials arranged to form at least a first pair of series connected vertically disposed back-to-back diodes.

25. A cell structure as defined in claim 24 including metal between said back-to-back diodes.

26. A cell structure as defined in claim 24, wherein said semiconductor materials are deposited semiconductor materials.

27. A cell structure as defined in claim 26, wherein said deposited semiconductor materials are amorphous semiconductor alloy materials.

28. A cell structure as defined in claim 27, wherein said amorphous semiconductor alloy materials include silicon.

29. A cell structure as defined in claim 27, wherein said amorphous semiconductor alloy materials include germanium.

30. A cell structure as defined in claim 27, wherein said amorphous semiconductor alloy materials include both silicon and germanium.

31. A cell structure as defined in claim 24 further including means for dividing said first pair of series connected vertically disposed back-to-back diodes into plural pairs of series connected vertically disposed back-to-back diodes.

32. A cell structure as defined in claim 31 including a separate portion of metal between the back-to-back diodes of each of said plural pairs of said back-to-back diodes.

33. A cell structure as defined in claim 24 further including a second plurality of vertically arrayed layers of semiconductor materials formed on said first plurality of vertically arrayed layers of semiconductor materials to form a second pair of series connected vertically disposed back-to-back diodes over said first pair of series connected vertically disposed back-to-back diodes.

34. A cell structure as defined in claim 33 further including means for dividing each said first and second pairs of series connected vertically disposed back-to-back diodes into first and second respective plural pairs of series connected vertically disposed back-to-back diodes.

35. A cell structure as defined in claim 34, wherein selected ones of said diodes of said first and second plural pairs of diodes are short circuited for forming a folded programmable logic array.

36. An integrated circuit comprising:

a multilayered structure of deposited layers of various materials including semiconductor alloy materials, said layers of semiconductor alloy materials being initially deposited as continuous layers, said layers being arranged to provide programmable semiconductor interactions between at least some of said layers so as to perform selected electrical functions at unique selected locations, and to provide said programmable semiconductor interactions in two separate subsets, each separately programmable from the other; and

addressing means for defining said unique selected locations and for enabling the programming of said semiconductor interactions of said semiconductor alloy material layers at said unique selected locations.

37. An integrated circuit as defined in claim 36, wherein said deposited semiconductor materials are amorphous semiconductor alloy materials.

38. An integrated circuit as defined in claim 37, wherein said amorphous semiconductor alloy materials include silicon.

39. An integrated circuit as defined in claim 37, wherein said amorphous semiconductor alloy materials include germanium.

40. An integrated circuit as defined in claim 37, wherein said amorphous semiconductor alloy materials include both silicon and germanium.

41. An integrated circuit as defined in claim 36, wherein at least one of said layers of semiconductor alloy material is a phase changeable material.

42. An integrated circuit as defined in claim 36, wherein said layers of semiconductor alloy materials initially form a pair of series coupled vertically disposed back-to-back diodes.

43. An integrated circuit as defined in claim 42 including metal between said back-to-back diodes.

44. An integrated circuit as defined in claim 42, wherein said addressing means forms means for dividing said pair of series connected vertically disposed back-to-back diodes into plural pairs of series connected vertically disposed back-to-back diodes.

45. An integrated circuit as defined in claim 44 including a separate portion of metal between the back-to-back diodes of each of said plural pairs of said back-to-back diodes.

46. An integrated circuit as defined in claim 36, wherein said addressing means comprises a first plurality of spaced apart address lines on one side of said multilayered structure and a second plurality of spaced apart address lines on the other side of said multilayered structure crossing said first plurality of address lines at an angle to form a plurality of crossover points defining said unique selected locations.

47. A programmable logic array comprising a multilayered structure of a plurality of vertically arrayed layers of various materials including deposited semiconductor alloy materials, said layers of semiconductor materials being initially deposited as continuous layers and at least some of said layers of various materials being arranged to provide semiconductor interactions between said layers for providing individually programmable selected logic functions across said structure at selected locations thereof;

and

means defining said selected locations and for enabling the programming of said selected logic functions at said selected locations.

48. A logic array as defined in claim 47, wherein said logic functions include AND and OR logic functions.

49. A logic array as defined in claim 47, wherein said layers of deposited semiconductor material form a pair of series coupled vertically disposed back-to-back diodes.

50. A logic array as defined in claim 49 including metal between said back-to-back diodes.

51. A logic array as defined in claim 47 including a pair of said multilayered structures, said structures being vertically arrayed to form a pair of programmable logic planes superposed one over the other.

52. A logic array as defined in claim 51, wherein said structures are programmed to provide an AND logic plane and an OR logic plane superposed one over the other.

53. A programmable logic array comprising a multilayered structure of a plurality of vertically arrayed layers of semiconductor materials to form a pair of series connected vertically disposed back-to-back diodes;

and means for dividing said pair of series connected vertically disposed back-to-back diodes into plural pairs of series connected vertically disposed back-to-back diodes and for enabling the short circuiting of selected ones of said diodes for programming groups of said diode pairs to provide selected logic functions.

54. A logic array as defined in claim 53 including a separate portion of metal between the back-to-back diodes of each of said plural pairs of said back-to-back diodes.

55. A logic array as defined in claim 53 including a pair of said multilayered structures, one superposed over the other, to form a folded programmable logic array.

56. A logic array as defined in claim 55, wherein the diode pairs of one of said structures are programmed to form an AND logic plane and the diode pairs of the other said structure are programmed to form an OR logic plane.

57. A solid state semiconductor programmable switch comprising a plurality of layers of semiconductor material to form at least two series connected vertically disposed cell portions;

said cell portions being individually programmable for permitting the conduction of current through said switch in only a first direction, or for permitting the conduction of current through said switch in only a second direction opposite said first direction, or for permitting the conduction of current through said switch in both said first and second directions;

or for preventing the conduction of current through said switch in either said first or second directions.

58. A programmable switch as defined in claim 57, wherein said cell portions comprise a pair of back-to-back diodes.

59. A programmable switch as defined in claim 58, wherein said cell portions are initially formed to prevent the conduction of current through said switch in either said first or second directions.

60. A method of programming a solid state semiconductor device having a plurality of semiconductor functions in series between a first and a second terminal, said semiconductor functions including a first subset which provides a relatively high impedance in a first direction along said series and a relatively low impedance in a second, opposite, direction along said series, and a second subset which provides a relatively high impedance in said second direction and a relatively low impedance in said first direction, said method comprising forming said device by depositing a plurality of layers of semiconductor material to provide said plurality of semiconductor functions, and selectively programming at least one semiconductor function of said first subset by applying a programming voltage across at least a portion of said device in said first direction.

61. A method of programming a solid state semiconductor device as described in claim 60, further comprising selectively programming at least one semiconductor function of said second subset by applying a programming voltage across at least a portion of said device in said second direction.

62. A method of programming a solid state semiconductor device as described in claim 60, wherein said applying of said programming voltage includes applying said voltage between said two terminals.

63. A method of programming a solid state semiconductor device as described in claim 60, wherein said device includes a third terminal, and said at least one semiconductor function of said first subset is between said first and third terminals and said at least one semiconductor function of said second subset is between said second and third terminals, and said applying of said programming voltage includes applying said programming voltage between said first and third terminals.

64. A method of programming a solid state semiconductor device as described in claim 60, wherein said semiconductor functions of said first and second subsets are provided by rectifying semiconductor junctions and said applying of said programming voltage includes applying a programming voltage of sufficient magnitude to cause a breakdown current across at least one said rectifying junction which provides said at least one semiconductor function of said first set.

65. A method of programming a solid state semiconductor device as described in claim 64, wherein said at least one rectifying junction includes phase changeable semiconductor material and said selectively programming said at least one semiconductor function of said first subset includes causing sufficient breakdown current to flow across said at least one rectifying junction so as to cause a phase change in the material of said junction.

66. An electrical circuit comprising:

a first conductor;

a second conductor; and

a programmable solid state semiconductor device connected between said first and second conductors, said device having a plurality of layers of semiconductor material to form a plurality of semiconductor junctions connected in electrical series between said conductors, said semiconductor junctions including a first subset which provides a relatively high impedance in a first direction along said series and a relatively low impedance in a second, opposite, direction along said series, and a second subset which provides a relatively high impedance in said second direction and a relatively low impedance in said first direction,

said circuit being originally formed with a relatively high impedance in both directions between said first and second conductors.

67. An electrical circuit as described in claim 66, wherein said programmable device includes two back-to-back diodes and wherein said first subset of semiconductor junctions include a rectifying semiconductor junction of a first of said back-to-back diodes and said second subset of semiconductor junctions includes a rectifying semiconductor junction of the other of said back-to-back diodes.

68. An electrical circuit as described in claim 67, wherein at least said first of said back-to-back diodes includes deposited, phase changeable semiconductor material.

69. An electrical circuit as described in claim 68, wherein said phase changeable material comprises an amorphous semiconductor alloy.

70. An electrical circuit as described in claim 69, wherein said alloy includes silicon.

71. An electrical circuit as described in claim 70, wherein said alloy includes hydrogen.

72. An electrical circuit as described in claim 70, wherein said alloy includes fluorine.

73. An electrical circuit as described in claim 69, wherein said alloy includes germanium.

74. An electrical circuit as described in claim 69, wherein said alloy includes both silicon and germanium.

75. An electrical circuit as described in claim 68 wherein said first diode includes a first layer of deposited semiconductor material of a first conductivity type, a second layer of deposited semiconductor material of a relatively intrinsic type which contacts said first layer, and a third layer of deposited semiconductor material of a second conductivity type which contacts said second layer.

76. An electrical circuit as described in claim 75, wherein the other of said back-to-back diodes includes a fourth layer of deposited semiconductor material of said first conductivity type, a fifth layer of deposited semiconductor material of a relatively intrinsic type which contacts said fourth layer, and a sixth layer of deposited semiconductor material of said second conductivity type which contacts said fifth layer.

77. An electrical circuit as described in claim 76, wherein the programmable device is formed on a substrate and the layers of deposited semiconductor material of said first diode are deposited over said substrate and the layers of deposited semiconductor material of said second diode are deposited over said layers of the first diode.

78. An electrical circuit as described in claim 77, wherein a layer of relatively conductive material is placed between said first and second diodes.

79. An electrical circuit as described in claim 78, wherein said relatively conductive material is a metal.

80. An electrical circuit as described in claim 78, further including conductive means connected to said relatively conductive material located between said first and second diodes for supplying a programming voltage and current to said relatively conductive material.

81. An electrical circuit as described in claim 68, wherein said first diode includes a portion of metal and said layer of semiconductor material forms a rectifying semiconductor junction with said portion of metal so as to provide said relatively high impedance in said first direction along said series and a relatively low impedance in said second, opposite, direction.

82. An electrical circuit as described in claim 81, wherein said other back-to-back diode includes an additional portion of metal and a layer of deposited semiconductor material which forms a rectifying semiconductor junction with said additional portion of metal so as to provide said relatively high impedance in said second direction and a relatively low impedance in said first direction.

83. An electrical circuit as described in claim 82, wherein the programmable device is formed on a substrate and the deposited semiconductor material of said first diode is deposited over said substrate and the deposited semiconductor material of said second diode is deposited over said semiconductor material of said first diode.

84. An electrical circuit as described in claim 83, wherein a layer of relatively conductive material is placed between said first and second diodes of said programmable device.

85. An electrical circuit as described in claim 84, wherein said layer of relatively conductive material is a metal which forms said rectifying junctions with the semiconductor material of both said first and second diodes.

86. An electrical circuit as described in claim 84, further including conductive means connected to said relatively conductive material located between said first and second diodes for supplying a programming voltage and current to said relatively conductive material.