Semiconductor memory

• US 4,646,267 A
• Filed: 04/22/1986
• Issued: 02/24/1987
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Ikuzaki, Kunihiko, Kawamoto, Hiroshi, Shimohigashi, Katsuhiro, Masuda, Hiroo
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/854,502
• Time in Patent Office: 308 Days
• Field of Search: 365/189, 365/190, 365/230, 365/149, 365/182
• US Class Current: 365/149
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETS formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory comprising:

at least one pair of data lines;

word lines arranged so as to traverse said data lines;

memory cells coupled in association with said data and word lines, each of said memory cells having a series connection of an MISFET and a capacitor;

a sense amplifier for amplifying a difference between signal levels appearing on said pair of data lines when the stored signal of the memory cell is read out, said sense amplifier comprising first and second circuits;

said first circuit including a pair of cross-coupled N-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation, and an N-channel MISFET coupled on the source side of said cross-coupled N-channel MISFETs for controlling the differential amplification operation of said cross-coupled N-channel MISFETs;

said second circuit including a pair of cross-coupled P-channel MISFETs coupled to said pair of data lines for bringing about a differential amplification operation, and a P-channel MISFET coupled on the source side of said cross-coupled P-channel MISFETs for controlling the differential amplification operation of said cross-coupled P-channel MISFETs; and

means for supplying first and second timing signals to the gates of said controlling N-channel and P-channel MISFETs, respectively so that the differential amplification operation of said cross-coupled N-channel MISFETs is started at a time different from the time when the differential amplification operation of said cross-coupled P-channel MISFETs is started.

2. A semiconductor memory according to claim 1, wherein said first timing signal occurs prior to the occurrence of said second timing signal so that a pair of said cross-coupled N-channel MISFETs begins its differential amplification operation prior to a pair of said cross-coupled P-channel MISFETs.

3. A semiconductor memory according to claim 1, wherein said second timing signal occurs prior to the occurrence of said first timing signal so that a pair of said cross-coupled P-channel MISFETs begins its differential amplification operation prior to a pair of said cross-coupled N-channel MISFETs.

4. A semiconductor memory according to claim 1, wherein said first circuit further includes another N-channel MISFET connected in parallel with said controlling N-channel MISFET.

5. A semiconductor memory according to claim 4, wherein said another N-channel MISFET has a conductance different from that of said controlling N-channel MISFET, wherein the gate of said another N-channel MISFET is supplied with a third timing signal.

6. A semiconductor memory according to claim 1, wherein said pair of data lines extend in parallel with each other, and wherein said first circuit is coupled on one end side of said pair of data lines while said second circuit is coupled on the other end side of said pair of data lines.

7. A semiconductor memory according to claim 1, wherein said MISFET of the memory cell is of the P-channel type.

8. A semiconductor memory according to claim 6, wherein said MISFET of the memory cell is of the P-channel type.

9. A semiconductor memory comprising:

a memory cell array including a plurality of data lines, a plurality of word lines, and a plurality of memory cells arrayed in association with said data and word lines;

each of said memory cells including an MISFET and a capacitor which are connected in series with each other, the gate of said MISFET being coupled to one of said word lines;

a plurality of sense amplifiers for amplifying a difference between signal levels appearing on a pair of adjacent ones of said data lines, each of said sense amplifiers including first and second sense circuits;

means for energizing said sense amplifiers, said energizing means including a first wiring to be provided with a first potential and a second wiring to be provided with a second potential higher than said first potential;

said first sense circuit comprising a pair of N-channel MISFETs which are cross-coupled to each other and are respectively coupled to said pair of data lines, and an N-channel MISFET coupled between said first wiring and said cross-coupled N-channel MISFETs for controlling operation of said cross-coupled N-channel MISFETs;

said second sense circuit comprising a pair of P-channel MISFETs which are cross-coupled to each other and are respectively coupled to said same pair of data lines, and a P-channel MISFET coupled between said second wiring and said cross-coupled P-channels MISFETs for controlling operation of said cross-coupled P-channel MISFETs; and

means for supplying first and second timing signals to the gates of said controlling N-channel and P-channel MISFETs, respectivley to turn on said controlling N-channel and P-channel MISFETs at different times, resulting in rendering the operation starting times of said first and second sense circuits different.

10. A semiconductor memory according to claim 9, wherein said first timing signal occurs prior to the occurrence of said second timing signal so that said first sense circuit begins its operation prior to said second sense circuit.

11. A semiconductor memory according to claim 9, wherein said second timing signal occurs prior to the occurrence of said first timing signal so that said second sense circuit begins its operation prior to said first sense circuit.

12. A semiconductor memory according to claim 9, wherein said MISFET of said memory cell is of P-channel type.

13. A semiconductor memory according to claim 12, wherein said first timing signal occurs prior to the occurrence of said second timing signal so that said first sense circuit begins its operation prior to said second sense circuit.

14. A semiconductor memory according to claim 9, wherein said data lines are arranged in the folded form in which each pair of adjacent ones of said data lines extend in parallel with each other from one of the both ends of said memory cell array to the other of said both ends while said word lines extend in a direction traversing said data lines, and wherein said first sense circuit is coupled to said pair of data lines at said one end of said memory cell array while said second sense circuit is coupled to said same pair of data lines at said other end of said memory cell array.

15. A semiconductor memory according to claim 14, wherein said MISFET of said memory cell is of the P-channel type.

16. A semiconductor memory according to claim 15, wherein said first timing signal occurs prior to the occurrence of said second timing signal so that said first sense circuit begins its operation prior to said second sense circuit.

17. A semiconductor memory according to claim 9, further comprising precharging circuit, each of which sets each pair of said data lines at a potential about intermediate between binary signal levels to be stored in each memory cell, before operation of the corresponding sense amplifier is started.

18. A semiconductor memory according to claim 17, wherein said first potential is a reference potential and said second potential is a positive voltage compared to the reference potential, wherein one of said binary signal levels to be stored in each memory cell is at the reference potential and the other is the positive voltage.

19. A semiconductor memory according to claim 18, wherein said MISFET of said memory cell is of the P-channel type.