Video graphic dynamic RAM

• US 4,646,270 A
• Filed: 09/15/1983
• Issued: 02/24/1987
• Est. Priority Date: 09/15/1983
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Voss, Donald J.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/532,330
• Time in Patent Office: 1,258 Days
• Field of Search: 365/230, 365/236, 365/239, 365/221, 365/78, 365/240, 365/238, 365/189, 364/200 MS File, 364/900 MS File
• US Class Current: 365/189.02
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

A memory chip containing a standard dynamic RAM having the capability to serially read out data at a high rate of speed while performing standard RAM operations is provided. A standard memory latches a complete row of data into a latch. The data from the latch is then transferred upon command to a second latch or shift register where it is shifted out independently of the operation of the RAM.

Claims

1. A monolithic memory capable of providing output data at a high speed, comprising:

a memory array;

a latch capable of latching a plurality of data bits, the latch being coupled to the memory array for temporarily storing data from the memory array;

a shift register capable of storing a plurality of data bits, the shift register being coupled to the latch for receiving the data temporarily stored in the latch; and

a multiplexer coupled to the shift register for selecting a predetermined data bit fron the shift register and for sequentially coupling the data out of the shift register to an output pin of the memory commencing with the predetermined data bit while data is simultaneously written/read into or out of the memory array.

2. The memory of claim 1 further including means for commanding the multiplexer to select the predetermined data bit.

3. The memory of claim 2 wherein the means for commanding is a decoder.

4. The memory of claim 1 wherein the latch and the shift register each handle the same number of data bits so that plurality in each case is equal to an integer n, and wheredn the multiplexer is an n-to-one multiplexer.

5. The memory of claim 4 wherein n equals 256.

6. The memory of claim 1 wherein the memory array is a dynamic random access memory (RAM).

7. A method of reading data out of a memory system at a high rate of speed, comprising:

latching a block of data from a memory array into a first temporary stroage, wherein the block of data contains a predetermined number of bits;

loading the block of data from the first temporary storage into a second temporary storage;

selecting a particular bit in the block of data in the second temporary storage to shift out first and then continuing shifting out data fron the second temporary storage in a sequential manner; and

reading/writing data into or out of the memory in a normal manner while the data is being shifted out of the second temporary storage.

8. The method of claim 7 further including latching another block of data in the first temporary storage during the time that the data is being shifted out of the second temporary storage.

9. A video display system having at least a memory system, and a controller to control operation of the video display system, the memory system comprising:

a memory array;

a latch coupled to the memory array for storing at least one row of data from the memory array, the latch being loaded upon a first command from the controller;

first means coupled to the latch for receiving the row of data from the latch upon a second command from the controller; and

second means for selecting a predetermined bit in the first means to commence serially shifting data out of the first means while access to the memory array can be simultaneously accomplished.

10. A video display system having at least a memory system, and a controller to control operation of the video display system, the memory system comprising:

a memory array;

a latch coupled to the memory array for storing at least one row of data from the memory array, the latch being loaded upon a first command from the controller;

first means coupled to the latch for receiving the row of data from the latch upon a second command from the controller; and

second means for selecting a predetermined bit in the first means to commence serially shifting data out of the first means wherein the second means includes an address latch for temporarily storing an address of the predetermined bit, a decoder for decoding the temporarily stored address, and a plurality of controllable means controlled by the decoder for serially coupling the data out of the first means.

11. A architecture for a high speed memory placed on an integrated circuit chip, the integrated circuit having a strandard dynamic random access memory (RAM) and further comprising:

first means for temporarily storing a block of data from the RAM;

second means coupled to the first means for controllably receiving the block of data from the first means;

a temporary storage for temporarily storing an address for a predetermined bit of data within the block of data;

a decoder coupled to the temporary storage for decoding the address of the predetermined bit; and

third means coupled to the second means and to the decoder for outputting the data of the second means upon command while allowing the RAM to be written into and read from in a normal manner during the time the data is being outputted from the second means and wherein the decoder provides the address of the predetermined bit to the second means.

12. The architecture for a high speed memory of claim 11 further including a counter located between the temporary storage and the decoder to coupled the address to be decoded from the temporary storage to the decoder and then to sequentially vary subsequent addresses which are decoded.

13. The architecture for a high speed memory of claim 11 wherein the first and second means are latches and the third means are a plurality of controllable gates which are individually controlled by the decoder.

14. The architecture for a high speed memory of claim 11 wherein the first means is a latch, the second means is a shift register, and the third means is a multiplexer.