Display device
First Claim
1. A display device comprising:
- a display element array having first m drive lines, second n drive lines and m×
n display elements arranged at intersections of said first m drive lines and said second n drive lines;
serial shift register means having a data input, a data output, and m×
n stages for storing pixel binary data, said m×
n stages divided into n blocks each having m stages, only a first block of said shift register means having m parallel outputs connected to said first m drive lines;
clock pulse signal supply means for supplying a clock pulse signal to said shift register means to shift pixel data through said shift register means, said clock pulse signal having intermittent pulse trains at intervals of a predetermined period, and each of said pulse trains having successive m clock pulses;
a serial pixel binary data source;
switch circuit means responsive to a select signal for selectively coupling one of said pixel data source and said data output of said shift register means to said data input of said shift register means;
first driving circuit means responsive to said m parallel outputs of said first block of said shift register means for driving said first m drive lines of said display element array; and
second driving circuit means responsive to said clock pulse supply means for sequentially driving said second n drive lines of said display element array;
wherein said second driving circuit means comprises,counter means for counting said clock pulses in said clock pulse signal from said clock pulse signal supply means, anddecoder means having n outputs coupled to said n drive lines of said display element array and responsive to said counter means for sequentially producing driving signals on said n outputs thereof to sequentially drive said n drive lines of said display element array every time said counter means counts m clock pulses in said clock pulse signal.
1 Assignment
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Accused Products
Abstract
A display device having a display array of m×n display elements driven by a static shift register having m×n stages respectively corresponding to row and column designations of the display elements. The column lines of the display element array are driven by a first output of the m stages. At the same time, pixel data are supplied to the shift register in accordance with a binary level of an externally supplied select signal. Alternatively, the shift register is shifted in a recursive manner. The row lines of the display element array are scanned in accordance with a count of a clock signal. Select signal lines and clock signal lines are respectively aligned along the row and column directions of a unit panel when plural display arrays as described above are arranged in a matrix form to provide a large-screen display unit. The lines of each display array are sequentially driven in accordance with the supply pattern of the select and clock signals from a corresponding unit driver. The shift register arrangement decreases the number of connections or wirings between a module driver and the display element array and simplifies the circuit arrangement of the module driver.
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Citations
5 Claims
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1. A display device comprising:
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a display element array having first m drive lines, second n drive lines and m×
n display elements arranged at intersections of said first m drive lines and said second n drive lines;serial shift register means having a data input, a data output, and m×
n stages for storing pixel binary data, said m×
n stages divided into n blocks each having m stages, only a first block of said shift register means having m parallel outputs connected to said first m drive lines;clock pulse signal supply means for supplying a clock pulse signal to said shift register means to shift pixel data through said shift register means, said clock pulse signal having intermittent pulse trains at intervals of a predetermined period, and each of said pulse trains having successive m clock pulses; a serial pixel binary data source; switch circuit means responsive to a select signal for selectively coupling one of said pixel data source and said data output of said shift register means to said data input of said shift register means; first driving circuit means responsive to said m parallel outputs of said first block of said shift register means for driving said first m drive lines of said display element array; and second driving circuit means responsive to said clock pulse supply means for sequentially driving said second n drive lines of said display element array; wherein said second driving circuit means comprises, counter means for counting said clock pulses in said clock pulse signal from said clock pulse signal supply means, and decoder means having n outputs coupled to said n drive lines of said display element array and responsive to said counter means for sequentially producing driving signals on said n outputs thereof to sequentially drive said n drive lines of said display element array every time said counter means counts m clock pulses in said clock pulse signal. - View Dependent Claims (2, 3)
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4. A display device comprising:
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a unit display panel having M×
N unit display devices arranged in a matrix form;clock pulse supply means having M output lines for sequentially providing clock pulse trains, each having successive m clock pulses, to said M output lines thereof, said M output lines of said clock pulse supply means being coupled to M groups of said unit display devices, respectively, and each of said M groups having N unit display devices; select signal supply means having N output lines for sequentially providing N select signals to said N output lines thereof, said N output lines of said select signal supply means being coupled to N groups of said unit display devices, respectively, and each of said N groups having M unit display devices; a common source of serial pixel binary data; and
each of said unit display devices including;a display element array having first m drive lines, second n drive lines and m×
n display elements arranged at intersections of said first m drive lines and said second n drive lines;serial shift register means having a data input, a data output, and m×
n stages for storing pixel binary data, said m×
n stages divided into n blocks each having m stages, only a first block of said shift register means having m parallel outputs;switch circuit means coupled to a corresponding output line of said select signal supply means and responsive to a select signal for selectively coupling one of said pixel data source and said data output of said shift register means to said data input of said shift register means; first driving circuit means responsive to said m parallel outputs of said first block of said shift register means for driving said first m drive lines of said display element array; and second driving circuit means coupled to a corresponding output line of said clock pulse supply means and responsive to clock pulses for sequentially driving said second n drive lines of said display element array, comprising, counter means for counting said clock pulses from said clock pulse signal supply means, and decoder means having n outputs coupled to said n drive lines of said display element array and responsive to said counter means for sequentially producing driving signals on said n output thereof to sequentially drive said n drive lines of said display element array every time said counter means counts m clock pulses. - View Dependent Claims (5)
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Specification