Storing video images on disk using video time base and retrieving the images using disk time base

• US 4,647,986 A
• Filed: 08/06/1984
• Issued: 03/03/1987
• Est. Priority Date: 08/06/1984
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Peters, Michael A., Gohde, Lewis J., Bergholz, Eugene W., Celek, John E., Vaughn, Steven T.
• Primary Examiner(s): Cardillo, Raymond F.
• Assistant Examiner(s): Weinhardt, Robert A.
• Application Number:
  US06/638,291
• Time in Patent Office: 939 Days
• Field of Search: 360/35.1, 360/32, 360/33.1, 358/342, 358/335, 358/111, 358/903, 364/200, 364/900
• US Class Current: 386/201
• CPC Class Codes: H04N 5/926 by pulse code modulation H04N5/919 takes precedence

Abstract

A multiple channel parallel transfer digital disk recorder is used to record digitized circular video images at the video frame rate. The digital pixel values for each image frame are written onto successive pages of a disk buffer memory (DBM) under video frame timing and are read from memory and written on disk under disk timing. When the last page image of the DBM is reached readout is switched back to the first page which is now filled with a frame of image data. Reading image data from disk and writing into successive pages of the DBM is done similarly. Only DBM locations containing pixels representative of actual image data within the circular boundaries of the image are addressed when reading from DBM and writing on disk and when reading from disk and writing onto DBM. Adjacent pixels in the image having predetermined bit lengths are written on disk with their bits in series. A group of adjacent pixels are written simultaneously and in coincident locations on the several disks under clocks that are derived from disk. A circuit is provided for correcting for the skew that can exist as a result of asynchronism between the timing of the disk. A programmable serial-to-parallel converter is provided for converting the serially recorded pixel of any bit length back to parallel bits of the same number as before they were serialized. The commands for the disk drive such as read, write, step and select cylinder are put in registers in response to occurrence of a disk index pulse for one multiple disk rotation and they are shifted to corresponding registers and are ready for execution when the next index pulse occurs so what is to be done by the disk drive during the next disk rotation is anticipated.

Claims

1. In a system wherein video camera analog video output signals representing images generated in correspondence with the rate of video frame timing signals are converted to digital data corresponding to the intensities of the picture elements (pixels) that compose the image in a video frame,

improved means for facilitating writing the digitized pixel data for consecutive video image frames on digital disk as the data for an image are produced and for reading said data from disk after it has been recorded, comprising:

magnetic disk recorder means having a plurality of coaxial magnetic disks jointly rotatable at constant speed, a plurality of read/write head trees, some heads in a tree arranged for magnetically coupling with the recording tracks of one disk and others for coupling with corresponding tracks on an adjacent disk for parallel transfer of digital data into and out of the respective disks,

a common radial position of all trees being defined as a cylinder, the disks being divided into sectors with a recorded signal for providing a sector pulse indicative of the beginning of each sector, means for providing an index pulse indicative of the beginning of each rotation of the disks, one of said disk having timing pulses recorded thereon for yielding timing pulses at a rate governed by said rotational speed of the disks, said timing pulses being asynchronous with said video frame timing signals, and actuator means responsing to command signals by positioning said trees and the heads thereof,

disk buffer memory (DBM) means comprised of a plurality of pages each of which has sufficient locations for storing the pixels composing one image and having data input and output means,

disk data processor (DDP) means including circuit means coupled to said read/write head means, respectively, and coupled to said disk buffer memory means, said DDP means being coupled to said disk buffer memory means, said DDP means being controlled at said video frame timing pulse rates derived from the disk and being operative when writing data from said DBM means onto disk to convert parallel pixel data to serial bit data that is transmitted in parallelism to corresponding read/write heads in the trees and operative when reading pixel data from the disk to convert serial pixel data from the respective read/write heads to parallel pixel data for being transferred to the DBM means,

memory controller means and bus means coupled to said DBM means for said controller means to provide simultaneous read and write pixel and buffer memory page addresses and control signals to said DBM means, said memory controller providing read addresses to one of said pages concurretly with providing write addresses to another of said pages, said memory controller being operative during image data transfer to write on disk to provide DBM means write addresses synchronous to video frame rate timing and to provide buffer memory read addresses synchronous to DDP timing, and during image data transfer reading from disk and writing into said DBM means to provide DBM reans write addresses synchronous to DDP timing, and to provide DBM read addresses synchronous to video frame timing,

a plurality of register means for storing digital commands for respectively establishing data paths, and containing data values, and storing control information,

video processor controller (VPC) means operative to load various ones of said registers with said commands with such loading of some commands in response to a said video frame synchronizing signal and concurrently loading others commands in response to a disk index synchronizing signal, and

digital disk controller (DDC) means including some of said registers for receiving commands for controlling the disk actuator and disk read-write operations on a disk rotation-by-rotation basis as well as controlling data flow through said disk data processor, said DDC being operative to load registers, respectively, with commands upon occurrence of an index pulse and to shift commands loaded after any one of said index pulses to a corresponding register for execution of the commands in response to the next index pulse that occurs.

2. The system according to claim 1 including means for effecting reading from said DBM and writing on disk only horizontal lines of pixels that are within the boundaries of the actual useful image stored in said DBM, comprising:

register means into which a Y-read start address is inserted for designating the first horizontal line in said DBM containing valid pixels comprising said useful image,

a Y-read counter for counting the horizontal lines from the first line and responsding to counting said first lines controling pixels by applying said Y-read start address to said DBM,

a memory for storing the sequence of addresses (X-read start addresses) at which readout of the pixels in each horizontal line is to start, said memory responding to said Y-read counter counting to said first line containing valid pixels by applying the first X-read start address to said DBM for said DBM to output the pixels in said line for being written on disk,

an X-read counter counting pixels, said counter being increment every time pixel data is transferred out of said DBM after the X-read start address is executed in a given horizontal line,

a digital comparator having an input for receiving the current X-address for any horizontal line,

a 2'"'"'s complementing device having an input for said X-read start address from said memory and an output coupled to an input of said comparator, said address corresponding to reading in the X-direction along any given horizontal line, said device producing the complement or negative equivalent of said X-read start address, said comparator responding to a comparison being made between said current X-read address and the 2'"'"'s complemented X-read start address by producing an end-of-X signal, and

means for transmitting said end-of-X signal to said Y-read counter to increment said Y-read counter and provide a new address to said X-read start memory for said memroy to generate the X-read start address for the next horizontal line.

3. The system according to claim 2 including means for reading image pixel data from disk and writing said data in said DBM, including:

a register that is loaded with a Y-write start address in contemplation of writing in said DBM, said Y-write start address being the address of the horizontal line on which data to be written is present,

means for providing an image-start signal corresponding to the read heads of said disk recorder being on the sector from which image data reading is to start,

a Y-write address counter having input means for receiving said image-start signal and for receiving the address of the first horizontal line to be written in said DBM, said address counter being incremented at the end of every horizontal line by and end-of-X signal,

an X-write start memory containing the X-write start addresses for each horizontal line, the count from said Y-write address counter being input to said X-write start nemory for determining the X-location of the first pixel that is to be written on the horizontal line,

an X-write counter to be loaded initially with a start address and then generating X-write start addresses by counting pixels and incrementing every time pixel data is transferred to said DBM after the X-write start address is executed,

a 2'"'"'s complementing device having an input for the X-write start address of the current horizontal line and having an output,

a comparator having an output and inputs for the current X-address and for the 2'"'"'s complement of said X-start address, said comparator responding to comparison of the inputs occurring by producing on end-of-X signal that is applied to increment said Y-write counter to produce the next downward horizontal line address.