Frequency doubler circuit and method

• US 4,648,021 A
• Filed: 01/03/1986
• Issued: 03/03/1987
• Est. Priority Date: 01/03/1986
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Alberkrack, Jade H.
• Primary Examiner(s): Salce, Patrick R.
• Assistant Examiner(s): Hoff, Marc S.
• Application Number:
  US06/815,963
• Time in Patent Office: 424 Days
• Field of Search: 307/267, 307/271, 328/20, 328/158, 363/157, 363/164, 363/165, 318/345 E
• US Class Current: 363/157
• CPC Class Codes: H02M 5/297 for conversion of frequency

Abstract

A frequency doubling circuit which produces a pair of pulses for each cycle of an input pulse applied thereto includes an inverter for producing a pulse that is inverted with respect to the applied input pulse. The inverted pulse is directly applied to a first input of an exclusive OR gate and a time delayed inverted pulse produced from the inverter output pulse is applied to a second input of the gate to produce the pair of pulses in response to the leading and trailing edges of the input pulse. The pair of pulses are then applied to a pulse stretching circuit which produces corresponding output pulses the pulsewidths of which are greater than the pulsewidths of the pulses applied thereto. A plurality of the frequency doubling circuits may be utilized to sequentially drive the pulse stretching circuit by OR'"'"'ing the outputs of the former to the latter. In such case a frequency doubling tachometer is realized that can be used in a closed loop DC Motor control system.

Claims

1. An integrated frequency doubling circuit having an input to which is supplied an input pulse and an output comprising:

a pulse doubling circuit responsive to the supplied input pulse for producing a pair of output pulses for each input pulse applied thereto; and

means for increasing the pulsewidth of pulses applied thereto, said means being coupled to said pulse doubling circuit and including a transistor having a base coupled to said pulse doubling circuit, a collector coupled to a terminal at which is supplied a ground potential, and an emitter coupled to a terminal of the frequency doubling circuit to which is connected a charge storage device, said transistor being rendered conductive by each of said output pulses from said pulse doubling circuit to discharge said charge storage device and then rendered non-conductive by the termination of each of said output pulses to permit charging of said charge storage device, and circuit means responsive to said charge storage device being discharged and then charging beyond a threshold voltage level for producing output pulses corresponding to each of said output pulses from said pulse doubling circuit applied to said means for increasing the pulsewidth, said output pulse having an increased pulse width with respect to said applied output pulses from said pulse doubling circuit.

2. An integrated circuit having at least three inputs to which are applied at least three input pulses in sequence, each pulse having a predetermined phase relationship with respect to each other pulse, the circuit providing a pair of output pulses at an output for each applied pulse, comprising:

first, second and third pulse doubling circuits each having an input coupled to a respective input of the circuit for producing a pair of pulses for each applied pulse;

means for sequentially Or'"'"'ing said pulses from said pulse doubling circuits at a first circuit node; and

means for increasing the pulsewidths of said pulses appearing at said first circuit node, said means for increasing the pulsewidths including a transistor having its base coupled to said first circuit node, its collector coupled to a first terminal at which is supplied ground potential and its emitter coupled to a second terminal, a capacitor coupled to said second terminal, said capacitor being discharged and then charged as said transistor is rendered conductive and then non-conductive in response to said pulses appearing at said first circuit node and inverter means coupled between said emitter and the output of the circuit for providing an output pulse for each pulse applied to said means for increasing the pulsewidths of said pulses, said pulsewidth of said output pulses being greater than that of said applied pulses.

3. A closed loop DC motor control system comprising detectors for providing a plurality of sequential phase related pulses corresponding to the rotational position of the rotor of the motor, a controller circuit responsive to said pulses for providing speed and drive control to the motor, a multiple input frequency doubling tachometer circuit which receives the sequential phase related pulses at respective inputs for providing a pair of pulses at an output corresponding to each pulse received at the respective inputs thereof, and integrator means coupled between said output of said frequency doubling tachometer circuit and an input of the controller circuit for providing a DC control voltage which is utilized by the controller circuit for maintaining a constant motor speed.

4. The control system of claim 3 wherein said frequency doubling tachometer circuit includes:

a plurality of frequency doubling circuits each one of said frequency doubling circuits having an input coupled to a respective input of said tachometer circuit and an output coupled to a common node and comprising a gate circuit having first and second inputs for producing a pair of pulses in response to a first pulse and a second pulse, time delayed with respect to said first pulse, being applied respectively to said first and second inputs, said gate circuit having an output coupled to said common node, circuit means coupled between said input of said frequency doubling circuit and said second input said gate circuit for providing time delay therethrough and conductive circuit means coupling said first input to said input of said frequency doubling circuit; and

a pulse stretching circuit coupled between said common node and said output of said frequency doubling tachometer for providing said pulses at said output of said frequency doubler tachometer having increased pulsewidths with respect to each of said pulses appearing at said common node from said output of each respective frequency doubling circuit.

5. The control system of claim 4 wherein said pulse stretching circuit includes:

a transistor having a base coupled to said common node, a collector coupled to a first terminal at which is supplied a ground reference, and an emitter coupled to a second terminal, said transistor being rendered conductive in response to each pulse occurring at said common node;

a RC network coupled to said second terminal including a capacitor which is discharged through said transistor and then charged to a voltage level when said transistor is non-conductive; and

an inverter responsive to the discharge and then the charging of said capacitor for producing said increased pulsewidth pulses at said output of said frequency doubling tachometer.