Bus interface device for a data processing system
First Claim
1. In a data processing system in which up to 2M data processing units are connected to a central control unit by a bus having M lines enabling bytes of M information bits to be exchanged between the data processing units and the central control unit, M is a positive integer, each of said data processing units and said central control unit include a bus interface mechanism, said bus interface mechanism comprising:
- M receiving circuits connected to different ones of the M bus lines respectively for resynchronizing and reshaping the train of bits received over each line, said bits being represented by a high or low voltage level within each bit period t, and each of said receiving circuits further comprising;
a first flip-flop, having a data input which receives the train of bits and an output which assumes the level of the input train of bits at the up-going transition of a first clock signal, provided by the central control unit, the period of which is twice the bit period, said flip-flop being reset at the down-going transition of said first clock signal,a second flip-flop, having a data input which receives the train of bits and an output which assumes the level of the input train of bits at the down-going transition of the first clock signal, said flip-flop being reset at the up-going transition of said clock signal, andan OR circuit having first and second inputs and which are connected to the outputs of said first and second flip-flops, respectively, and which provides at an output a train of resynchronized bits.
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Accused Products
Abstract
A bus interface device for a data processing system in which 2M units are interconnected and exchange information bits over a bus comprising at least M lines.
The device comprises a receiving circuit associated with each respective line (D0-D7) of the bus and including two flip-flops 40 and 41 that assume the voltage level on the input line at the up-going and down-going transitions of a clock signal (CLK1) and are restored at the down-going and up-going transitions of that signal. When the bits received over the bus are encoded in the NRZ code, using a bit period equal to half a period of the clock signal, OR circuit 47 provides at its output the resynchronized train of input bits received over D0-D7.
The 2M units are divided into two groups, with the units in each group requesting access to the bus during either phase of a second clock signal (CLK2). When the bus is free, flip-flops 48 and 49 provide an indication of the requests for access to the bus made by the associated units.
39 Citations
3 Claims
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1. In a data processing system in which up to 2M data processing units are connected to a central control unit by a bus having M lines enabling bytes of M information bits to be exchanged between the data processing units and the central control unit, M is a positive integer, each of said data processing units and said central control unit include a bus interface mechanism, said bus interface mechanism comprising:
- M receiving circuits connected to different ones of the M bus lines respectively for resynchronizing and reshaping the train of bits received over each line, said bits being represented by a high or low voltage level within each bit period t, and each of said receiving circuits further comprising;
a first flip-flop, having a data input which receives the train of bits and an output which assumes the level of the input train of bits at the up-going transition of a first clock signal, provided by the central control unit, the period of which is twice the bit period, said flip-flop being reset at the down-going transition of said first clock signal, a second flip-flop, having a data input which receives the train of bits and an output which assumes the level of the input train of bits at the down-going transition of the first clock signal, said flip-flop being reset at the up-going transition of said clock signal, and an OR circuit having first and second inputs and which are connected to the outputs of said first and second flip-flops, respectively, and which provides at an output a train of resynchronized bits. - View Dependent Claims (2, 3)
- M receiving circuits connected to different ones of the M bus lines respectively for resynchronizing and reshaping the train of bits received over each line, said bits being represented by a high or low voltage level within each bit period t, and each of said receiving circuits further comprising;
Specification