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Bus interface device for a data processing system

  • US 4,648,102 A
  • Filed: 03/05/1984
  • Issued: 03/03/1987
  • Est. Priority Date: 03/29/1983
  • Status: Expired due to Fees
First Claim
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1. In a data processing system in which up to 2M data processing units are connected to a central control unit by a bus having M lines enabling bytes of M information bits to be exchanged between the data processing units and the central control unit, M is a positive integer, each of said data processing units and said central control unit include a bus interface mechanism, said bus interface mechanism comprising:

  • M receiving circuits connected to different ones of the M bus lines respectively for resynchronizing and reshaping the train of bits received over each line, said bits being represented by a high or low voltage level within each bit period t, and each of said receiving circuits further comprising;

    a first flip-flop, having a data input which receives the train of bits and an output which assumes the level of the input train of bits at the up-going transition of a first clock signal, provided by the central control unit, the period of which is twice the bit period, said flip-flop being reset at the down-going transition of said first clock signal,a second flip-flop, having a data input which receives the train of bits and an output which assumes the level of the input train of bits at the down-going transition of the first clock signal, said flip-flop being reset at the up-going transition of said clock signal, andan OR circuit having first and second inputs and which are connected to the outputs of said first and second flip-flops, respectively, and which provides at an output a train of resynchronized bits.

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