Dynamic memory controller for single-chip microprocessor

• US 4,649,511 A
• Filed: 07/25/1983
• Issued: 03/10/1987
• Est. Priority Date: 07/25/1983
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Gdula, Michael
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): CHAN, EMILY Y
• Application Number:
  US06/516,620
• Time in Patent Office: 1,324 Days
• Field of Search: 365/222, 365/233, 364/200 MS File
• US Class Current: 711/106
• CPC Class Codes: G06F 9/4825 Interrupt from clock, e.g. time of day
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A controller for interfacing a single-chip microcomputer with external dynamic random-access memory, includes a subcircuit for generating a column-address strobe at a time after a row-address strobe is generated, and also includes a multiplexing subcircuit for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8-bit dynamic memory inputs, prior to receipt of the associated row-address or column-address strobe. The microprocessor utilizes the strobe-generation and multiplexing subcircuits to burst-refresh the dynamic memory, in one presently preferred embodiment. In another presently preferred embodiment, lines from an additional microprocessor output port are utilized with a resettable binary counter and a multiplicity of buffers, to count through the range of row addresses in cyclic fashion, with each address being incremented after the previously-addressed row of memory cells has been refreshed.

Claims

1. In combination, dynamic memory means for storing one bit of each of a plurality of data words in each cell along one of a plurality of rows each containing a multiplicity of said cells, said dynamic memory means requiring periodic refreshment, within a maximum time interval, of at least one cell along each of said rows, and including a plurality N of address inputs for designating at least the row of said memory means to be addressed;

single-chip microprocessor means internally containing at least a cpu and an internal memory, for utilization of the data stored into said dynamic memory means, which is external to said microprocessor means, and including means for providing a periodic clock signal timing means for causing a refresh sequence for the external memory means to be initiated at a time not longer than the maximum time interval after a previous refreah sequence has been initiated;

means for periodically providing a single external memory enable signal during each of a sequential multiplicity of operational cycles of said miroprocessor means;

at least two output ports of N bit-lines each; and

refresh-addressing means for presenting a refresh row designation data to at least one designated one of said output ports responsive to an initiation of a refresh sequence by said timing means; and

address means, activated directly and solely by said clock signal and said single external memory enable signal and responsive to said timing means initiating said refresh sequence, for sequentially addressing at least one cell along each of said plurality of memory means rows to refresh the information stored in all cells along that memory row having the cell then being addressed;

said address means including;

multiplexing means for selectively connecting each of the N bit-lines of said at least one designated one of the microprocessor means output ports to the associated one of the row-designating N inputs of said dynamic memory means, with the designation of the one output port of said microprocessor means then connected being responsive to different states of a selection signal; and

logic means for providing the selection signal state responsive only to receipt of both said clock signal and said external memory enable signal from said microprocessor means, including a first flip-flop logic element having a clock input receiving said clock signal, a data input receiving said external memory enable signal, and an output providing said selection signal and having an output state determined by both the state of the data input signal and the occurrence of a first pulse of said clock signal exit clock input; and

said memory means accepts thr ow designation data at said address inputs responsive to a row-address strobe signal generated by a change in said external memory enable signal prior to another pulse of said clock signal, occurring after said first clock signal pulse.

2. The combination of claim 1, wherein said logic means further includes a second flip-flop logic element having a clock input receiving said clock signal, a data input receiving the inversion of said selection signal from the output of said first flip-flop logic element, and an output providing a column-address strobe signal responsive to the state of said data input when an additional pulse of said clock signal occurs at said second flip-flop logic element clock input at a selected time after the occurrence of said another clock signal pulse.

3. The combination of claim 2, wherein said memory means is adapted to allow selection of data stored in one cell along a previously-selected one of said plurality of rows responsive to a plurality of data bits presented at said plurality N of memory means address inputs when said column-address strobe signal is received;

said microprocessor means is adapted to provide, prior to the occurrence of said column-address strobe signal, column designation data at another of the at least two output ports; and

said first flip-flop logic element output changes the state of the selection signal prior to said additional clock signal pulse, to cause said multiplexing means to connect each of the N bit-lines of the another output port to the associated one of the plurality N of memory means addressing inputs prior to reception of the column-address strobe signal.

4. In combination, dynamic memory means for storing one bit of each of a plurality of data words in each cell along one of a plurality of rows each containing a multiplicity of said cells, said dynamic memory means requiring periodic refreshment, within a maximum time interval, of at least one cell along each of said rows;

and including a plurality N or address inputs for receiving data, responsive to a row-address strobe signal, for designating at least the row of said memory means to be addressed;

single-chip microprocessor means internally containing at least a CPU and an internal memory, for utilization of the data stored in said dynamic memory means, which is external to said microprocessor means, and including means for providing a periodic clock signal;

timing means for causing a refresh sequence for the external memory means to be initiated at a time not longer than the maximum time interval after a previous refresh sequence has been initiated;

means for periodically providing a single external memory enable signal during each of a sequential multiplicity of operational cycles of said microprocessor means; and

means for providing a clearing signal which is normally enabled and is temporarily disabled, for the duration of a refresh sequence, responsive to said timing means determining that a refresh sequence is required; and

address means, activated directly and solely by said clock signal and said single external memory enable signal and responsive to said timing means initiating said refresh sequence, for sequentially addressing at least one cell along each of said plurality of memory means rows to refresh the information stored in all cells along that memory row having the cell then being addressed, and including;

a first flip-flip logic element having a clock input receiving said clock signal, a data input receiving said external memory enable signal, and an output having an output state determined by both the state of the data input signal and occurrence of a first pulse of said clock signal at said clock input;

means for generating said row-address strobe signal responsive to a change in said external memory enable signal prior to another pulse of said clock signal, occurring after said first clock signal pulse;

a second flip-flop logic element having a clock input receiving said closk signal, a data input receiving the inversion of the output signal of said first flip-flop logic element, and an output providing a column-address strobe signal responsive to the state of said data input when a different pulse of said clock signal occurs at said second flip-flop logic element clock input at a selected time after the occurrence of said another clock signal pulse;

counter means for sequentially counting, with one count change being responsive to each occurrence of said column-address strobe signal, through a plurality of different ouput states, equal at least to the number of the plurality of row addresses, said counter means being cleared to a lowest count responsive to the enablement of said clearing signal and enabled to count responsive to the disablement of said clearing signal; and

means for providing the output count of said counter means to the plurality of memory means address inputs for designating the row of said memory means to be addressed.

5. The combination of claim 4, wherein a first of said row-address strobe signals is provided to said memory means only after said lowest count has been provided to said memory means address inputs from said counting means.

6. The combination of claim 5, wherein each subsequent row-address strobe signal is provided only after the count in said counting means has been changed, responsive to a column-address strobe signal, and the changed count has been provided to said memory means address inputs.

7. The combination of claim 4, wherein said microcomputer means is adapted to cease other operations when said counter means is enabled to count and to resume said other operations responsive to said counter means reaching a predetermined count.

8. The combination of claim 4, wherein said microprocessor means has at least two output ports of N bit lines each, and further comprising multiplexing means for selectively connecting each of the N bit-lines of only one designated one of the at least two microprocessor means output ports to the associated one of the row-designating N inputs of said dynamic memory means, with the designation of the one output port of said microprocessor means then connected being responsive to different states of a selection signal provided at the output of said first flip-flop logic element;

said multiplexing means being effectively disconnected from said memory means address inputs whenever said clearing signal is disabled.

9. A controller for interfacing external dynamic memory means for storing each bit of a plurality of data words in one of a plurality of cells along each of a plurality of rows each containing a multiplicity of said cells, and having a plurality N of address input lines for designating at least the memory means row responsive to a row-address strobe signal, and a microprocessor, having a CPU and an internal memory and having at least two output ports, each containing at least a plurality N of bit-lines at which at least external memory addressing data is provided, with the microprocessor providing only a periodic clock signal and an external memory enable signal, along with said at least external memory addressing data, to said controller;

said controller comprising;

multiplexing means for selectively connecting each of N selected bit-lines of a designated one of the microprocessor output ports to a predetermined on of the N address inputs of the external dynamic memory means;

that one of the plurality of microprocessor means output ports then being connected to said memory means being designated responsive to a selected one of a plurality of different states of a selection signal; and

logic means for providing the selection signal state responsive to receipt of both said clock signal and said external memory enable signal, and including;

a first flip-flop logic element having a data input receiving said external memory enable signal, a clock input receiving said clock signal and an output providing said selection signal and having each of the plurality of different states determined by both the state of the data input signal and the occurrence of a first pulse of said clock signal at said clock input, and means for providing said row-address strobe signal responsive only to a change in the external memory enable signal prior to another pulse of said clock signal occurring after said first clock signal pulse.

10. The controller of claim 9, wherein said external dynamic memory means determines the particular cell along the designated row responsive to column address data present at said plurality N of address inputs and responsive to the presence of a column-address strobe signal;

said logic means further including a second flip-flop logic element having a clock input receiving said clock signal, a data input receiving the inversion of the selection signal and the output of said first flip-flop logic element, and an output providing said column-address strobe signal responsive to the state of input when an additional pulse of said clock signal occurs at said second flip-flop logic element clock input at a selected time after the occurrence of said another clock signal pulse.

11. The controller of claim 10, further comprising counter means for sequentially counting, with one count change being responsive to each occurrence of said column-address strobe signal, through a plurality of different output states, equal at least to the number of the plurality of row addresses of said external dynamic memory means, said counter means being cleared to a lowest count responsive to the enablement of a clearing signal and enabled to count responsive to the disablement of said clearing signal;

said multiplexing means being enabled by said clearing signal; and

means for providing the output count of said counter means to the plurality of external memory means address inputs for designating the row of said memory means to be addressed.

12. The controller of claim 11, wherein a first of said row-address strobe signals is provided to said external memory means only after said lowest count has been prov:

ded to said external memory means address inputs from said counting means.

13. The controller of claim 12, wherein each subsequent row-address strobe signal is provided only after the count in said counting means has been changed, responsive to a column-address strobe signal, and the changed count has been provided to said external memory means address inputs.

14. The controller of claim 12, wherein said microprocessor is adapted to disable said clearing signal whenever refreshment of said external memory means is required, and said controller includes means for providing a signal to said microcomputer responsive to said counter means reaching a predetermined count.

15. The controller of claim 14, wherein said microprocessor is adapted to enable said clearing signal when said predetermined count signal is received.