Interface circuit having a shift register inserted between a data transmission unit and a data reception unit

• US 4,649,512 A
• Filed: 07/18/1983
• Issued: 03/10/1987
• Est. Priority Date: 07/16/1982
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Nukiyama, Tomoji
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Niessen, William G.
• Application Number:
  US06/514,902
• Time in Patent Office: 1,331 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/200, 364/900, 377/66, 377/81, 377/77, 377/71, 377/73, 377/51, 377/54
• US Class Current: 710/305
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 5/08 having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register G06F5/065 takes precedence; shift registers per se G11C19/00

Abstract

An interface unit for connecting a transmitting unit to a receiving unit, the transmitting being capable of transmitting data at a speed greater than the processing speed of the receiving unit. The interface includes a serially connected multistage register which receives input data from the transmitting unit at its input stage and reads out data stored in its output stage to the receiving unit. It also includes a control circuit and a counter storing a count corresponding to the quantity of data stored in the register, the counter being incremented by one each time data is added to the register and decremented by one each time data is read from the register output stage. The control circuit is composed of a decoder and write control circuit. The decoder provides a signal to the write control circuit indicative of the count in the counter. When a datum is to be received from the transmitting unit, it signals the interface through a gate circuit, this signal incrementing the memory. This increment is sensed by the decoder which enables the write control circuit to cause the input data to be written into the first available register stage closest to the output stage. When the register is full, this information is provided to the transmitting unit by the decoder to inhibit the generation of additional data to the interface until an empty stage is available in the register.

Claims

1. An interface circuit inserted between a data transmission unit and a data reception unit comprising a shift register having a plurality of serially coupled register stages, each register stage having a data input gate, a data storage means for storing data applied thereto through the data input gate, and a data output gate, first means for applying a write control signal in common to the data input gates of said register stages to turn on each data input gate, a second means for supplying a read control signal in common to the data output gates of said register stages to turn on each data output gate, a first bus coupled to the first register stage of said shift register for applying data from said data transmission unit to said input gate of said first register state, a second bus coupled to the last register stage of said shift register for deriving data stored in the last register, a counter counting the number of data applied to said first register stage through said first bus, and a control circuit coupled to said shift register and said counter and applying said write control signal to the output gate or gates of such register stage or stages that is selected by the output of said counter at the same time when said write control signal is applied to the data input gates of the register stages in common, whereby both the data input gate and the data output gate of the selected register stage or stages are simultaneously turned on by said write control signal to directly transfer a data through said selected register stage or stages.

2. An interface circuit as claimed in claim 1, further comprising means for receiving a data transfer request signal from said data transmission unit, said receiving means being coupled to said counter to increase the count number according to the received data transfer request signal.

3. An interface circuit as claimed in claim 1, wherein said counter decreases the count number according to said read control signal.

4. An interface circuit comprising a shift register having a plurality of register stages serially coupled to each other, a first means coupled to an initial register stage of said shift register for applying data in serial to said shift register, a second means coupled to a last register stage of said shift register for deriving data in serial therefrom, each register stage having an input gate, a storage means and an output gate, a third means coupled in common to the input gate of each register stage for turning on the input gate of each register stage simultaneously with a first signal, a fourth means coupled to the output gate of each register stage for turning on the output gate of each register stage by a second control signal at different timing when the input gate of each register is turned on by said first signal, a fifth means for designating at least one of said plurality of register stages through which a data applied thereto is to be transferred, and a sixth means coupled to said shift register and to said fifth means for applying said first signal to the output gate or gates of the designated register stage or stages when said input gates of said register stages are simultaneously turned on with said first signal by said third means.

5. An interface circuit as claimed in claim 4, wherein the data applied from said first means is written into a register stage subsequent to said designated register stage or stages through said designated register stage or stages.