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Interface circuit having a shift register inserted between a data transmission unit and a data reception unit

  • US 4,649,512 A
  • Filed: 07/18/1983
  • Issued: 03/10/1987
  • Est. Priority Date: 07/16/1982
  • Status: Expired due to Term
First Claim
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1. An interface circuit inserted between a data transmission unit and a data reception unit comprising a shift register having a plurality of serially coupled register stages, each register stage having a data input gate, a data storage means for storing data applied thereto through the data input gate, and a data output gate, first means for applying a write control signal in common to the data input gates of said register stages to turn on each data input gate, a second means for supplying a read control signal in common to the data output gates of said register stages to turn on each data output gate, a first bus coupled to the first register stage of said shift register for applying data from said data transmission unit to said input gate of said first register state, a second bus coupled to the last register stage of said shift register for deriving data stored in the last register, a counter counting the number of data applied to said first register stage through said first bus, and a control circuit coupled to said shift register and said counter and applying said write control signal to the output gate or gates of such register stage or stages that is selected by the output of said counter at the same time when said write control signal is applied to the data input gates of the register stages in common, whereby both the data input gate and the data output gate of the selected register stage or stages are simultaneously turned on by said write control signal to directly transfer a data through said selected register stage or stages.

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