Apparatus for synchronizing linear PN sequences

• US 4,649,549 A
• Filed: 07/18/1984
• Issued: 03/10/1987
• Est. Priority Date: 08/30/1983
• Status: Expired due to Term

• Current Assignee: Choice Technology Inc., PAUL E. HAUG (18%), R., SIG Technology AG (SIG Group AG)
• Original Assignee: SOPHISTICATED SIGNALS AND CIRCUITS
• Inventors: Koos, William M. Jr., Mallory, Peter E., Haug, Paul E., Halpern, Peter H.
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US06/632,001
• Time in Patent Office: 965 Days
• Field of Search: 375/1, 375/2.2, 375/106, 375/114, 375/115, 375/118, 375/119, 375/120, 178/22.17
• US Class Current: 380/32
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

A system and method are disclosed for synchronizning the linear PN sequences contained in a received spread spectrum signal, characterized by the provision of a resident PN generator that is responsive to the chip rate clock for producing a replica of the PN sequence with arbitrary phase, a running matrix inverse of the matrix (R) formed by n successive observations of the register of the resident generator, and a matrix vector product device for multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector. These estimates are smoothed and averaged to produce the smoothed phase vector (c_j) that is applied to one input of a dot product device that operates in conjunction with the contents of the shift register of the resident generator to produce the properly phased PN sequence, which sequence is then supplied to despreading means for combining the noisy chips with the properly phased PN sequence. The system may be used for range computation, if desired.

Claims

1. Apparatus for synchronizing the linear PN sequences contained in the heavy noise background of a receiver data-carrying spread spectrum signal, comprising

(a) demodulator means (106, 109) for separating from the received signal the noisy wideband PN spread spectrum component, and for generating a chip rate clock signal;

(b) resident PN generator means (110) responsive to said chip rate clock signal for producing a replica of the PN sequence with arbitrary phase;

(c) running matrix inverse means (112) for obtaining the inverse (R^-1) of the matrix (R) that is formed by n successive observations of the register of the resident generator;

(d) matrix vector product means (118) for multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector;

(e) means (122) for smoothing and averaging the phase vector estimates, thereby to produce the smoothed phase vector (c_j);

(f) dot product means (114) responsive to said smoothed phase vector and to the contents of the resident shift register for producing the properly phased PN sequence; and

(g) despreading means (108) for combining the noisy chips with the properly phased PN sequence, whereby the narrowband digital data carried by the spread spectrum signal may be recovered.

2. Apparatus as defined in claim 1, and further including phase delay computer means (130) for converting the smoothed phase vector to actual phase delay, thereby affording range computation.

3. Apparatus as defined in claim 1, wherein said matrix vector product means includes

(1) a plurality of AND gates having output terminals, first input terminals [d₁ . . . d_n ] receiving the data signals, and second input terminals connected with corresponding D stages of the running matrix inverse (R_ij, where j=1 through n, i=1 through n);

(2) a plurality of mod 2 adders connected with the output terminals of a plurality of said AND gates, respectively, thereby to provide a plurality of phase vector estimates, respectively;

(3) means for smoothing the individual components of the phase vector; and

(4) threshold means for deciding polarity of the individual phase vector components.

4. Apparatus as defined in claim 3, wherein said smoothing means comprises an up/down counter.

5. Apparatus as defined in claim 3, wherein said smoothing means comprises an up/down accumulator, and zero counter means for determining the amount by which the up/down accumulator is incremented or decremented.

6. Apparatus as defined in claim 1, wherein said resident PN generator means (110) includes a shift register (4), and recursion means connected with said shift register for producing the next bit depending on the n prior bits, said recursion means having a plurality of known coefficients of recursion (X₁ . . . X_n-1);

and further wherein said running matrix inverse means includes a plurality of columns i (where i=1 . . . m) each including

(1) a plurality of D stage registers (14);

(2) a plurality of mod 2 adders (12) connected between said registers, respectively;

(3) a plurality of AND gates (10) having outputs connected with said mod 2 adders, respectively, each of said AND gates having a pair of input terminals;

(4) means for applying said known coefficients of recursion (X₁ . . . X_n-1) to one input terminal of said AND gates, respectively;

(5) means for applying to the other input terminal of each of said AND gates a feedback signal provided by a connection between the output of the last D stage and the input of the first D stage of said column; and

(6) means for loading in parallel to the D stages of each column, respectively, second signals (Y_li . . . Y_ni) that are known a'"'"' priori functions of said coefficients of recursion, thereby loading the initial inverse (R_o^-1).

7. Apparatus as defined in claim 6, wherein the initial inverse matrix has the form ##EQU61##

8. Apparatus as defined in claim 1, wherein said resident PN generator means includes

(1) a plurality of D stage registers (314);

(2) a plurality of mod 2 adders (312) connected between said registers, respectively;

(3) a plurality of AND gates (310) having outputs connected with said mod 2 adders, respectively, each of said AND gates having a pair of input terminals;

(4) means for applying said known coefficients of recursion (X₁ . . . X_n-1) to one input terminal of said AND gates, respectively; and

(5) means for applying to the other input terminal of each of said AND gates a feedback signal provided by a connection between the output of the last D stage and the input of the first D stage of said column;

and further wherein said running matrix inverse means includes a plurality of columns i (where i=1 . . . m) each including

(1) a shift register (304), and recursion means connected with said shift register for producing the next bit depending on the n prior bits, said recursion means having a plurality of known coefficients of recursion (X₁ . . . X_n-1); and

(2) means for loading in parallel to the D stages of each column, respectively, second signals (Y_1i . . . Y_ni) that are known a'"'"' priori functions of said coefficients of recursion, thereby loading the initial inverse (R_o^-1).

9. Apparatus as defined in claim 1, wherein said running matrix inverse means (112) includes a plurality of rows i (where i=1 . . . m), each of said rows including

(1) a plurality of D stage registers (404);

(2) a plurality of mod 2 adders (412) connected between said registers, respectively;

(3) a plurality of AND gates (410) having outputs connected with said mod 2 adders, respectively, each of said AND gates having a pair of input terminals;

(4) means for applying said known coefficients of recursion (X₁ . . . X_n-1) to one input terminal of said AND gates, respectively;

(5) means for applying to the other input terminal of each of said AND gates a feedback signal providing by a connection between the output of the last D stage and the input of the first D stage of said row; and

(6) means for loading in parallel to the D stages of each row, respectively, second signals (Y_i1 . . . Y_in) that are known a'"'"' priori functions of said coefficients of recursion, thereby loading the initial inverse (R_o^-1).

10. Apparatus as defined in claim 5, wherein said zero counter means is operable to count also the number and weight of soft decisions which are used in each matrix vector dot product, thereby to obtain a more accurate up-date of the accumulation.

11. The method for synchronizing the linear PN sequences contained in the heavy noise background of a received data-carrying spread spectrum signal, comprising the steps of

(a) demodulating the received signal to separate therefrom the noisy widebank PN spread spectrum component and to generate a chip rate clock signal;

(b) producing by resident PN generator means in response to the chip rate signal a replica of the PN sequence with arbitrary phase;

(c) obtaining the running matrix inverse (R_o^-1) of the matrix (R) that is formed by n successive observations of the shift register of the resident PN generator means;

(d) multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector;

(e) smoothing and averaging the phase vector estimates to produce the smoothed phase vector (c_j);

(f) producing from the smoothed phase vector and the contents of the resident generator shift register a properly phased PN sequence; and

(g) combining the noisy chips with the properly phased PN sequence, thereby to permit recovery of the narrowband digital data carried by the spread spectrum signal.

12. The method as defined in claim 11, and further including the step of delaying the phase of the smoothed averaged phase vector for use in range computation.

13. The method as defined in claim 12, and further including the step of combining phase-advanced adn phase-retarded versions of the properly phased PN sequence to produce a combined control signal (V₁ -V₂) for synchronizing the chip rate clock.