Method of fabricating silicon-on-insulator transistors with a shared element

• US 4,649,627 A
• Filed: 06/28/1984
• Issued: 03/17/1987
• Est. Priority Date: 06/28/1984
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Stiffler, Scott R., Abernathey, John R., Lasky, Jerome B., Kinney, Wayne I.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): QUACH, TUAN N
• Application Number:
  US06/625,758
• Time in Patent Office: 992 Days
• Field of Search: 29/576 E, 29/571, 29/580, 357/68, 357/23.7, 357/81, 148/DIG. 135, 148/DIG. 164, 148/175, 148/DIG. 150
• US Class Current: 438/153
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: Y10S 148/135 Removal of substrate
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer is defined into another FET with its drain region above the gate oxide, whereby the drain region also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.

Claims

1. A method of fabricating a semiconductor structure, comprising the steps of:

depositing an epitaxial semiconductor layer on a first side of a first semiconductor substrate;

forming a silicon oxide layer of predetermined thickness on said epitaxial layer;

bonding said first side of said substrate to a second semiconductor substrate using said silicon oxide layer as a bonding material, thereby forming a bonded structure;

removing said first substrate from said bonded structure to expose a major surface of said epitaxial layer;

removing said epitaxial layer in selected areas to form active device regions of said epitaxial layer;

forming a field oxide on areas of said epitaxial layer other than said active device regions;

forming a gate oxide on areas of said epitaxial layer over said active device regions;

forming a conductive gate electrode over a predetermined portion of said gate oxide;

defining and forming SOI source and drain regions in said epitaxial layer on either side of said gate electrode, said SOI regions having a conductivity type the opposite of said epitaxial layer; and

defining and forming bulk source and drain regions in portions of said second substrate on either side of at least one of said SOI source and drain regions, said bulk regions having a conductivity type opposite the conductivity type of said second substrate.

2. A method of fabricating a semiconductor structure as recited in claim 1, wherein said epitaxial layer and said second substrate have the same conductivity type.

3. A method of fabricating a CMOS semiconductor structure as recited in claim 1, wherein said epitaxial layer and said second substrate have opposite conductivity types.

4. A method of fabricating a semiconductor structure as recited in claim 1, further comprising the steps of:

removing said epitaxial layer in selected areas to form active device regions of said epitaxial layer;

forming a field oxide on areas of said epitaxial layer other than said active device regions;

forming a conductive gate electrode over a predetermined portion of said gate oxide;

defining and forming SOI source and drain regions in said epitaxial layer on either side of said gate electrode, said SOI regions having a conductivity type the opposite of the conductivity type of said epitaxial layer; and

defining and forming bulk source and drain regions in portions of said second substrate on either side of at least one of said SOI source and drain regions, said bulk regions having a conductivity type opposite the conductivity type of said second substrate.

5. A method of fabricating a semiconductor structure as recited in claim 4, wherein said epitaxial layer and said second substrate have the same conductivity type.

6. A method of fabricating a CMOS semiconductor structure as recited in claim 5, wherein said epitaxial layer and said second substrate have opposite conductivity types.

7. A method of fabricating a semiconductor structure, comprising the steps of:

depositing an epitaxial semiconductor layer on a first semiconductor substrate of the opposite conductivity type from said epitaxial layer;

forming a silicon oxide layer of a predetermined thickness on a second semiconductor substrate;

bonding said second semiconductor substrate on said epitaxial layer of said first semiconductor substrate at a predetermined temperature in an oxidizing atmosphere using said silicon dioxide layer as the bonding material, thereby forming a bonded structure;

removing said first substrate from said bonded structure to expose a major surface of said epitaxial layer;

forming a masking layer on said epitaxial layer;

patterning said masking layer to cover preselected active device regions;

removing portions of said epitaxial layers exposed by said patterned masking layer;

removing said masking layer;

forming a gate oxide and gate electrode over a predetermined portion of said epitaxial layer;

defining and forming epitaxial source and drain regions of a conductivity type opposite to the conductivity type in said epitaxial layer; and

defining and forming source and drain regions in regions of said second semiconductor substrate adjacent and on either side of one of said epitaxial source and drain regions, said source and drain regions having a conductivity type opposite the conductivity type of said second substrate.

8. A method of forming a plurality of transistors having a shared element, comprising the steps of:

depositing an epitaxial semiconductor layer on a first side of a first semiconductor substrate;

bonding said first said of said first substrate to a first side of a second semiconductor substrate having a first insulating layer disposed on its first side to form a bonded structure;

removing said first semiconductor substrate from said bonded structure to expose a major surface of said epitaxial layer;

forming an insulating layer on a upper surface of said etched epitaxial layer;

etching selected portions of said epitaxial layer;

forming isolation regions on exposed portions of said second substrate;

forming a layer of conductive material on said isolation regions and said insulating layer;

etching said layer of conductive material, defining and forming first source and drain regions in portions of said epitaxial layer exposed by etching said layer of conductive material, said layer of conductive material forming a first gate electrode that cooperates with said first source and drain regions to form a first FET device; and

defining and forming second source and drain regions in portions of said second substrate on either side of a selected one of said first source and drain regions, said selected one of said first source and drain regions forming a second gate electrode that cooperates with said second source and drain regions to form a second FET device.