Logic data transfer bus preloading circuit

• US 4,651,036 A
• Filed: 02/21/1985
• Issued: 03/17/1987
• Est. Priority Date: 02/24/1984
• Status: Expired due to Term

• Current Assignee: Societe Pour L'Etude et La Fabrication Des Circuits Integres Speciaux Efcis
• Original Assignee: Societe Pour L'Etude et La Fabrication Des Circuits Integres Speciaux Efcis
• Inventors: Tallaron, Louis
• Primary Examiner(s): Heyman, John S.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US06/703,885
• Time in Patent Office: 754 Days
• Field of Search: 323/315, 323/316, 307/443, 307/270, 307/478, 307/574, 307/581, 307/269, 307/452, 307/453, 307/246, 307/572, 307/579, 307/584, 307/448, 330/288
• US Class Current: 326/86
• CPC Class Codes: G06F 13/4077 Precharging or discharging
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data transfer bus preloading circuit including a large sized transistor r ensuring rapid bus conductor preloading. This transistor is conductive at the beginning of the preloading step proper, but is blocked as the bus voltage reaches the desired preload value which corresponds to the sum of the respective threshold voltages of two other transistors of the circuit. The circuit includes five field effect transistors, two supply terminals, a preloading control input terminal and a preloading inhibiting input terminal. The large size transistor is connected between a first supply terminal and the output terminal of the circuit. A second transistor is connected between the gates of the first and third transistors. The gate of the second transistor is connected to the preloading control input terminal. The third transistor is connected between the source terminal and the fifth transistor. The gate and source of the third transistor are connected together. The fourth transistor is connected between the ground supply terminal and the gate of the first transistor. The gate of the fourth transistor is connected to the preloading inhibiting input terminal. The fifth transistor is connected between the third transistor and the ground supply terminal. The gate of the fifth transistor is connected to the output of the circuit. It is also possible to add a sixth transistor between the fifth transistor and the ground supply terminal with the drain and gate of this transistor being connected together.

Claims

1. A logic data transfer bus conductor preloading circuit comprising two supply terminals, an output terminal adapted to be connected to said bus conductor, a preloading control input terminal and a preloading inhibiting input terminal, wherein said preloading circuit further comprises a first transistor connected between a first supply terminal and said output terminal, a second transistor connected between the gate of said first transistor and the source of a third transistor, the gate of said second transistor being controlled by the preloading control input, and the drain of said third transistor being connected to the first supply terminal, a fourth transistor connected between the gate of said first transistor and a second supply terminal, the gate of said fourth transistor being controlled by said preloading inhibiting input terminal, a fifth transistor connected in series between the source of said third transistor and said second supply terminal, the gate of said fifth transistor being connected to said output terminal.

2. A preloading circuit according to claim 1, which further comprises a sixth transistor connected in series between said fifth transistor and said second supply terminal, the drain of said sixth transistor being connected to the gate thereof.

3. A preloading circuit according to claim 1, wherein said third transistor is a depletion layer transistor the gate of which is connected to the source thereof.