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Logic data transfer bus preloading circuit

  • US 4,651,036 A
  • Filed: 02/21/1985
  • Issued: 03/17/1987
  • Est. Priority Date: 02/24/1984
  • Status: Expired due to Term
First Claim
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1. A logic data transfer bus conductor preloading circuit comprising two supply terminals, an output terminal adapted to be connected to said bus conductor, a preloading control input terminal and a preloading inhibiting input terminal, wherein said preloading circuit further comprises a first transistor connected between a first supply terminal and said output terminal, a second transistor connected between the gate of said first transistor and the source of a third transistor, the gate of said second transistor being controlled by the preloading control input, and the drain of said third transistor being connected to the first supply terminal, a fourth transistor connected between the gate of said first transistor and a second supply terminal, the gate of said fourth transistor being controlled by said preloading inhibiting input terminal, a fifth transistor connected in series between the source of said third transistor and said second supply terminal, the gate of said fifth transistor being connected to said output terminal.

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