Programmed disk controller capable of operating with a variety of data encoding techniques

• US 4,651,237 A
• Filed: 06/28/1984
• Issued: 03/17/1987
• Est. Priority Date: 06/28/1984
• Status: Expired due to Term

• Current Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Original Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Inventors: Williams, Brady G.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/625,461
• Time in Patent Office: 992 Days
• Field of Search: 364/200, 364/900, 360/40, 360/48
• US Class Current: 360/48
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11B 20/1419 to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
• CPC Class Codes: G11B 20/1423 Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
• CPC Class Codes: G11B 20/1426 conversion to or from block codes or representations thereof
• CPC Class Codes: G11B 2020/10537 Audio or video recording
• CPC Class Codes: G11B 2220/2508 Magnetic discs

Abstract

A disk controller system utilizes a single state machine having random access memory which is loaded with program code to translate between computer data and signals obtained by reading from, or developed for writing onto, a magnetic disk in accordance with a selected data encoding technique. The encoding techniques that are discussed include FM, MFM, GCR and RLL. Different program code is loaded into the state machine'"'"'s memory to make the controller operate with each of these techniques.

Claims

1. A computer system disk controller adapted to transfer digital data between a computer and magnetic data storage media read/write head means, comprising:

means including a programmable state machine for translating between digital data of the computer system and signals in a form placed onto said magnetic storage media;

said state machine including a signal input line, a signal output line, a random access memory having an address input of a plurality of bit lines and data output of a plurality of bit lines, said signal input line being connected to one of said address bit lines, a latch having an input of a plurality of bit lines and an output of a plurality of bit lines, said signal output line being connected to one of the latch output bit lines, a bus connecting the memory data output bit lines with the latch input bit lines, a bus connecting a plurality of the latch output bit lines with a plurality the memory address input bit lines,

means selectively connecting said state machine signal input and output lines between the computer and the head means for causing the controller to operate in either a data read or write mode, and

means for programming said state machine to select one of a plurality of specific magnetic media signal formats that are translated by said translating means, whereby said controller can interface a given computer with a magnetic storage system having one of said plurality of magnetic signal formats.

2. The controller according to claim 1 wherein said specific magnetic signal formats include FM, MFM, GCR and RLL formats.

3. The controller according to claim 1 wherein the programmable state machine of said translating means includes a random access memory, and wherein said programming means includes means for loading said random access memory with computer code of a selected one of said plurality of signal formats.

4. The controller according to claim 1 wherein said memory data loading means includes means for introducing the data and its addresses though said bus connecting the memory data output bit lines with the latch input bit lines.

5. The controller according to claim 1 which additionally comprises a microcomputer connected to control its operation, said microcomputer having a plurality of input/output lines connected to a plurality of said memory address bit lines.