Vector data processor
First Claim
Patent Images
1. A vector data processor, comprising:
- (a) a main storage;
(b) operation means for sequentially performing an operation on vector elements provided to said operation means in such a manner as to provide vector elements corresponding to the results of said operation in parallel to receiving new vector elements;
(c) a plurality of vector registers each being selected by an instruction, each being accessible independently from each other vector register, and each including means connected to said main storage and said operation means so as to receive vector elements therefrom or to provide vector elements thereto for holding a plurality of vector elements at a plurality of address locations within each vector register;
(d) control means connected to control said vector registers and responsive to instructions, including a plurality of write counter means each connected to a corresponding vector register, for sequentially indicating addresses of said storage locations within the corresponding vector register at which a write operation is to be effected for vector elements received by the corresponding vector register when the corresponding vector register is selected by an instruction so as to receive the vector elements, and including a plurality of read counter means each connected to a corresponding vector register and operable simultaneously with said write counter means connected to said corresponding vector register, for sequentially indicating addresses of storage locations at which a read operation is to be effected for vector elements held by the corresponding vector register when the corresponding vector register is selected by an instruction so as to read the held vector elements.
0 Assignments
0 Petitions
Accused Products
Abstract
A vector data processor includes a vector index register for consecutively and sequentially storing indirect address vectors, which may then be consecutively and sequentially read out from the vector index register to form addresses of data, thereby to execute the consecutive reading of the data from a main storage and the consecutive writing thereof into the main storage with an increased processing speed by generating addresses and storing data in overlapping operations.
-
Citations
19 Claims
-
1. A vector data processor, comprising:
-
(a) a main storage; (b) operation means for sequentially performing an operation on vector elements provided to said operation means in such a manner as to provide vector elements corresponding to the results of said operation in parallel to receiving new vector elements; (c) a plurality of vector registers each being selected by an instruction, each being accessible independently from each other vector register, and each including means connected to said main storage and said operation means so as to receive vector elements therefrom or to provide vector elements thereto for holding a plurality of vector elements at a plurality of address locations within each vector register; (d) control means connected to control said vector registers and responsive to instructions, including a plurality of write counter means each connected to a corresponding vector register, for sequentially indicating addresses of said storage locations within the corresponding vector register at which a write operation is to be effected for vector elements received by the corresponding vector register when the corresponding vector register is selected by an instruction so as to receive the vector elements, and including a plurality of read counter means each connected to a corresponding vector register and operable simultaneously with said write counter means connected to said corresponding vector register, for sequentially indicating addresses of storage locations at which a read operation is to be effected for vector elements held by the corresponding vector register when the corresponding vector register is selected by an instruction so as to read the held vector elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 15, 16)
-
-
8. A vector data processor, comprising:
-
storage means for storing plural sets of vector elements; a plurality of vector registers each having a plurality of addressable memory locations and being connected to said storage means so as to receive vector elements from or provide vector elements to said storage means; control means connected to said plurality of vector registers and responsive to an instruction for sequentially writing vector elements provided to said plurality of vector registers into plural memory locations of a vector register when the vector register is selected by the instruction to receive the vector elements and responsive to an instruction for sequentially reading vector elements held by a vector register when the vector register is selected by the instruction to provide the held vector elements; arithmetic means connected to said plurality of vector registers for performing an arithmetic operation on first vector elements read out sequentially from one of said vector registers selected by an instruction which requires execution of the arithmetic operation and for sequentially providing a vector register with vector elements corresponding to the result of the arithmetic operation; and access means connected to said vector registers and said storage means for performing an operation on second vector elements read out sequentially from one of said vector registers selected by an instruction which requires execution of an access by said access means to provide corresponding to the results of the operation by said access means data signals as a sequence of addresses for said storage means and for sequentially accessing said storage means with the sequence of addresses to fetch and provide third vector elements having the sequence of addresses among the plural sets of vector elements from said storage means to a selected vector register. - View Dependent Claims (9, 10, 11, 12, 13, 14, 17, 18)
-
-
19. A vector data processor, comprising:
-
storage means for storing plural sets of vector elements; a plurality of vector registers each having a plurality of addressable memory locations and being connected to said storage means so as to receive vector elements from or provide vector elements to said storage means; control means connected to said plurality of vector registers and responsive to an instruction for sequentially writing vector elements provided to said plurality of vector registers into plural memory locations of a vector register when the vector register is selected by the instruction to receive the vector elements and responsive to an instruction for sequentially reading vector elements held by a vector register when the vector register is selected by the instruction to provide the held vector elements; arithmetic means connected to said plurality of vector registers for performing an arithmetic operation on first vector elements read out sequentially from a first vector register selected by an instruction which requires execution of the operation by said arithmetic means and for sequentially providing a second vector register selected by the instruction which requires the arithmetic operation with vector elements corresponding to the result of the operation so that the vector elements are written into the second vector register; and access means connected to said vector registers and said storage means for performing an operation on second vector elements read out sequentially from one of said vector registers selected by an instruction which requires execution of an access by said access means to generate a sequence of addresses for third vector elements stored in said storage means and for sequentially accessing said storage means with the generated sequence of addresses to fetch and provide the third vector elements from said storage means to a third vector register selected by the instruction which requires execution of an access so that the third vector elements are written into the third vector register.
-
Specification