Forming memory transistors with varying gate oxide thicknesses

• US 4,651,406 A
• Filed: 06/04/1986
• Issued: 03/24/1987
• Est. Priority Date: 02/27/1980
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Shimizu, Shinji, Komori, Kazuhiro, Kosa, Yasunobu, Sugiura, June
• Primary Examiner(s): Ozaki, George T.
• Application Number:
  US06/873,056
• Time in Patent Office: 293 Days
• Field of Search: 29/591, 29/571, 29/576 B, 29/577 C, 148/1.5, 148/187
• US Class Current: 438/275
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

A semiconductor integrated circuit device and a method of manufacturing the same, wherein an MIS type memory transistor of a two-layered gate electrode structure is formed on the surface of a semiconductor substrate, and an MIS type transistor for a low voltage having a comparatively thin gate oxide film and an MIS type transistor for a high voltage having a comparatively thick gate oxide film are formed around the memory transistor.

Claims

1. A method of manufacturing a semiconductor integrated circuit device comprising first type MIS transistors capable of operating at high voltage and second type MIS transistors, capable of operating at low voltage, comprising the steps of:

(a) preparing a semiconductor substrate having a first conductivity type region, said first conductivity type region having a major surface;

(b) forming an insulating region dividing said major surface into first and second areas on which to form said first type MIS transistors and said second type MIS transistors, respectively;

(c) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said second area through an insulating film formed over the second area without introducing said impurity into said first area;

(d) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said first and second areas simultaneously through an insulating film, serving as a gate insulating film, formed over the first and second areas so as to have a thin thickness portion over said second area and a thick thickness portion over said first area;

(e) forming a plurality of gate electrodes on said insulating film serving as the gate insulating film so as to exist over each of said first and second areas; and

(f) forming source and drain regions associated with each of said plurality of gate electrodes in said first and second areas by introducing an impurity of the opposite conductivity type to the conductivity type of said first conductivity type region into said first and second areas, said plurality of source and drain regions forming said first type MIS transistors and said second type MIS transistors with said plurality of gate electrodes in said first and second areas, respectively.

2. A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said insulating region is formed by oxidation of said main surface of the first conductivity type region.

3. A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said impurity is introduced by an ion implantation process.

4. A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said plurality of gate electrodes are formed from a high-melting point metal.

5. A method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said plurality of gate electrodes are formed from a polycrystalline silicon layer.

6. In a method of manufacturing a semiconductor integrated circuit device comprising preparing a first conductivity type region having a major surface;

forming an insulating region dividing said major surface into a first area and a second area; and

forming a plurality of MIS type transistors in said first area and in said second area, said plurality of MIS type transistors including first type MIS transistors capable of operating at high voltage formed in said first area and second type MIS transistors capable of operating at low voltage formed in said second area, the improvement comprising the steps of;

(a) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said second area through an insulating film formed over the second area without introducing said impurity into said first area;

(b) introducing an impurity of the same conductivity type as the conductivity type of said first conductivity type region into said first and second areas simultaneously through an insulating film, serving as a gate insultating film, formed over the first and second areas so as to have a thin thickness portion over said second area and a thick thickness portion over said first area;

(c) forming a plurality of gate electrodes on said insulating film serving as the gate insulating film so as to exist over each of said first and second areas; and

(d) forming source and drain regions associated with each of said plurality of gate electrodes in said first and second areas by introducing an impurity of the opposite conductivity type to the conductivity type of said first conductivity type region into said first and second areas, said plurality of source and drain regions forming said first type MIS transistors and said second type MIS transistors with said plurality of gate electrodes and said first and second areas, respectively.