Fabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies

• US 4,651,408 A
• Filed: 05/17/1984
• Issued: 03/24/1987
• Est. Priority Date: 01/05/1984
• Status: Expired due to Term

• Current Assignee: STMicroelectronics NV
• Original Assignee: Northern Telecom Limited (Nortel Networks Corporation)
• Inventors: White, James J., Calder, Iain D., MacElwee, Thomas W.
• Primary Examiner(s): SABA, WILLIAM
• Application Number:
  US06/611,549
• Time in Patent Office: 1,041 Days
• Field of Search: 29/571, 29/576 J, 29/576 B, 29/576 E, 29/576 T, 29/578, 29/580, 148/1.5, 148/175, 148/DIG. 164, 148/DIG. 91, 156/612, 357/23.7, 357/23.9, 357/41, 357/42, 357/44, 357/59
• US Class Current: 438/152
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: Y10S 148/091 Laser beam processing of fets
• CPC Class Codes: Y10S 148/164 Three dimensional processing

Abstract

In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided.

Claims

1. A process for the fabrication of vertically integrated MOS devices comprising the ordered steps of:

forming field oxide regions on a semiconductor substrate;

forming a first gate oxide region on the substrate;

forming a gate on the first oxide region;

forming a second gate oxide region over the gate;

depositing a polycrystalline semiconductor layer over the gate and oxide regions so as to directly contact the substrate of at least one contact position;

heating, melting and then cooling the polycrystalline on the substrate to promote lateral seeding thereof from the substrate semiconductor at the or each contact position; and

after lateral seeding of the polycrystalline, forming sources and drains in both the substrate and recrystallized polycrystalline semiconductor by ion implantation using a plurality of separate implants at different energies to achieve desired concentration of ions at a desired depth within the recrystallized and substrate silicon.

2. A process as claimed in claim 1 in which the semiconductor is silicon.

3. A process as claimed in claim 2 further comprising melting the polysilicon and the silicon substrate at a seeding source region near a contact position using a laser.

4. A process as claimed in claim 3 further comprising moving a laser beam away from the seeding source region near a contact position to encourage seeding above the gate.

5. A process as claimed in claim 2 in which the second gate oxide region is etched at a predetermined location to provide a window at which the subsequently deposited polysilicon layer contacts the substrate silicon at said contact position.

6. A process as claimed in claim 5 particularly for forming a CMOS inverter in which the window is vertically aligned with the subsequently formed drains.

7. A process as claimed in claim 2 in which the gate is formed of doped, laser-recrystallized polysilicon.

8. A process as claimed in claim 2 in which each vertically integrated MOS device is formed within a device well bounded by regions of field oxide wherein the field oxide is relatively thin, being of the order of 0.5 microns thick.

9. A process as claimed in claim 1 in which, following implantation of ions to form said sources and drains, the wafer is subjected to a laser annealing step to activate said ions.

10. A process as claimed in claim 2 in which regions of said polysilicon layer are doped and laser annealed to establish conducting paths from sources, drains and gate of said device to bonding pads at remote locations of the substrate.

11. A process as claimed in claim 1 wherein the step of forming sources and drains comprises using a single mask for each of said implants.

12. A proocess as claimed in claim 11 further including laser annealing after said sources and drains are formed to render the implanted ions active.