Method of fabricating a high density, low power, merged vertical fuse/bipolar transistor

• US 4,651,409 A
• Filed: 09/03/1985
• Issued: 03/24/1987
• Est. Priority Date: 02/09/1984
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: NCR Corporation
• Inventors: Sullivan, Paul A., Ellsworth, Daniel L.
• Primary Examiner(s): Roy, Upendra
• Assistant Examiner(s): Callahan, John T.
• Application Number:
  US06/771,855
• Time in Patent Office: 567 Days
• Field of Search: 29/576 B, 29/578, 29/576 C, 148/1.5, 148/DIG. 55, 156/644, 427/93, 357/2, 357/0.4, 357/51, 357/52, 357/59, 365/96, 365/104
• US Class Current: 438/207
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/10 ROM devices comprising bipolar components
• CPC Class Codes: Y10S 148/055 Fuse

Abstract

A fuse programmable ROM includes a wafer for a CMOS-type structure having an emitter, which emitter is overlain by a fuse pad of an undoped polysilicon and a conductive layer. There is a layer of barrier oxide disposed on the conductive top layer of the fuse pad and a sidewall oxide surrounding the periphery of the fuse pad both of which are overlain by the metallic electrical connection.

The process of producing the fuse programmable ROM includes wide utilization of standard CMOS fabrication techniques with which are included the steps of depositing fuse material of undoped polysilicon, forming the fuse material into a fuse pad, and then making an electrical connection with the fuse pad.

Claims

1. A process of fabricating at least one electrically programmable read only memory element comprising the steps of:

forming a wafer for CMOS-type structures having a polysilicon gate and having a first conductivity type base contact region in a second conductivity type epitaxial layer, the first conductivity type base contact region being juxtaposed to a field oxide layer which partially overlies the second conductivity type region;

forming an active first conductivity type base region extending to the first conductivity type base contact region by blanket implantation;

depositing a layer of isolation oxide over the wafer;

masking the isolation oxide except in an area over the active base region;

etching the isolation oxide exposed by the masking down to the first conductivity type active base region to define an emitter contact area on the active base region;

doping the emitter contact area with second conductivity type impurity;

annealing the wafer to form a second conductivity type diffused emitter;

depositing an undoped polysilicon layer over the second conductivity type diffused emitter;

forming a second conductivity type doped polysilicon layer one the exposed surface of the polysilicon layer;

masking the polysilicon layer except in the areas over and adjacent to the emitter contact area and etching the unmasked areas to form a fuse pad of the undoped polysilicon covering the emitter contact areas and having a periphery overlying the isolation oxide;

providing an interfacial barrier layer on the surface of the fuse pad;

opening contact areas to the first conductivity type base contact region;

depositing metal over the fuse pad and contact areas to form electrical connections for the memory element; and

passifying the resulting element.

2. The process of claim 1 wherein the step of providing the interfacial barrier layer is comprised of forming a layer of tungsten which is selectively deposited on the fuse pad and the first conductivity type base contact region immediately prior to depositing metal to form the electrical connections therewith.

3. The process recited in claim 2, further including after the step of masking and etching the polysilicon layer the additional step of depositing a layer of silicon dioxide over the entire wafer and etching the layer of silicon dioxide away to leave a protective deposit of silicon dioxide in abutment with the periphery of the fuse pad.