Channel monitoring circuit for use in a repeater station over radio digital transmission

• US 4,653,070 A
• Filed: 09/06/1985
• Issued: 03/24/1987
• Est. Priority Date: 09/11/1985
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Hashimoto, Hiromi, Nakajima, Masahiro
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/773,161
• Time in Patent Office: 564 Days
• Field of Search: 375/3, 375/4, 375/10, 455/7, 455/8, 455/9, 455/10, 455/17, 371/22, 371/48, 371/49, 364/514, 340/825.06, 340/825.16, 370/13, 370/17, 370/55
• US Class Current: 714/800
• CPC Class Codes: H04B 17/40 of relay systems
• CPC Class Codes: H04L 1/24 Testing correct operation

Abstract

In radio digital transmission system including at least one repeater station, a channel monitoring circuit of each repeater station comprises, besides the conventional inter-terminals fault detection circuit using parity check system, a control bit inserting circuit for inserting a parity control bit into the received signal, a control bit extracting circuit for extracting the control bit from the received signal, a logic circuit for logically operating the output signal of the conventional fault detection circuit and the output signal of the control bit extracting circuit, and a second fault detecting circuit responsive to the output signal of the logic circuit for detecting the fault on the transmitting line between the repeater station and an immediately preceding station.

Claims

1. A channel monitoring circuit for use in a repeater station of a radio digital transmission system comprising:

an input terminal supplied with a digital input signal from a receiving unit of said repeater station;

a counter connected to said input terimal for counting a number of mark signals contained in a data section having a predetermined number of time slots;

a check bit extracting circuit connected to said input terminal for extracting a parity check pit from said input signal;

a comparator for comparing output signals of said counter and said check bit extraction circuit;

a first fault detecting circuit responsive to an output signal of said comparator for detecting a fault on said transmission system between a transmitting station and said repeater station;

a control bit inserting circuit for inserting into a time slot of said input signal said output of said comparator to act as a parity control bit;

an output terminal connected to said control bit inserting circuit for sending said input signal inserted with said parity control bit to a transmitting unit of said repeater station;

a control bit extracting circuit for extracting a content of said time slot for said parity control bit from said input signal;

a logic circuit supplied with an output signal of said control bit extracting circuit and an output signal of said comparator for logically operating these output signals to produce a signal representing occurrence of a fault; and

a second fault detecting circuit responsive to an output signal of said logic circuit for detecting a fault on said transmitting system between the repeater station and an immediately preceding station.

2. The channel monitoring circuit according to claim 1 wherein each of said input and output terminals has N parallel terminals which are directly interconnected except one input terminal and one output terminal, said one input terminal being connected to input terminals of said check bit extracting circuit, said control bit extracting circuit and said control bit inserting circuit and said one output terminal being connected to an output terminal of said control bit inserting circuit.

3. The channel monitoring circuit according to claim 1 wherein an output signal of said comparator represents a coincidence or noncoincidence of said two input signals.

4. The channel monitoring circuit according to claim 1 which further comprises an alarm and display device connected to receive output signals of said first and second fault detectors.